Three-dimensional non-volatile semiconductor memory device having replacement gate

Abstract

The disclosed technology relates generally to semiconductor devices and more particularly to three dimensional semiconductor memory devices, such as vertical three dimensional non-volatile memory devices. In one aspect, a vertical three-dimensional semiconductor memory device comprises a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell. The semiconductor memory device additionally includes at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.

What is claimed is: 
     
         1 . A vertical three-dimensional semiconductor memory device, comprising:
 a memory block comprising at least one memory hole formed through a stack of alternating layers of control gate layers and dielectric layers, wherein the memory hole is filled with a plurality of materials forming at least one memory cell; and   at least one trench formed through the stack so as to define part of a boundary of the memory block, wherein a sidewall of the trench comprises the control gate layers each having at least a portion that is in part laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.   
     
     
         2 . The memory device of  claim 1 , wherein the control gate layers comprise semiconductor layers, and wherein the electrically conductive material comprises a metallic material. 
     
     
         3 . The memory device of  claim 1 , wherein the electrically conductive material comprises one or more of tungsten, tungsten nitride, tantalum, tantalum nitride, titanium, and titanium nitride. 
     
     
         4 . The memory device of  claim 1 , wherein the memory block is formed on a substrate, and wherein the at least one memory hole has a pillar shape having a circular cross section when viewed in a direction substantially perpendicular to a main surface of the substrate. 
     
     
         5 . The memory device of  claim 1 , wherein the memory hole is a V-shaped trench. 
     
     
         6 . The memory device of  claim 1 , wherein the trench forms the boundary of the memory block. 
     
     
         7 . The memory device of  claim 1 , wherein the memory cell materials are formed on the sidewall of the at least one memory hole. 
     
     
         8 . The memory device of  claim 7 , wherein the memory cell materials comprise a sidewall stack comprising a programmable material, a channel material, and a dielectric material. 
     
     
         9 . The memory device of  claim 1 , wherein the electrically conductive material forms electrically conductive plugs. 
     
     
         10 . The memory device of  claim 1 , wherein the recessed portions of the control gate layers are partly recessed such that remaining portions of the control gate layers are laterally interposed between the recessed portions and the memory cell materials. 
     
     
         11 . A three-dimensional (3D) semiconductor memory device, comprising:
 a memory hole formed vertically through a stack comprising gate electrode lines alternating with dielectric layers, wherein a memory layer stack is formed on a sidewall of the memory hole; and   a trench formed laterally adjacent to the memory hole and vertically through the stack, wherein a sidewall of the trench comprises the gate electrode lines each having at least a portion that is partly laterally recessed relative to vertically adjacent dielectric layers, and wherein the trench is filled with an electrically conductive material.   
     
     
         12 . The 3D semiconductor memory device of  claim 11 , wherein the electrically conductive material has a lower electrical resistivity than the gate electrode lines. 
     
     
         13 . The 3D semiconductor memory device of  claim 11 , wherein a plurality of memory holes are formed laterally between a pair of trenches in a length direction of the gate electrode lines. 
     
     
         14 . The 3D semiconductor memory device of  claim 11 , wherein the memory layer stack comprises a programmable material formed on the sidewall of the memory hole and a semiconductor channel material formed on the programmable material. 
     
     
         15 . The 3D semiconductor memory device of  claim 11 , wherein the memory hole is a circular hole and the memory layer stack lines a circular sidewall of the memory hole. 
     
     
         16 . The 3D semiconductor memory device of  claim 15 , wherein the trench is a circular trench and the memory hole and the circular trench are laterally surrounded by the gate electrode lines and the dielectric layers. 
     
     
         17 . The 3D semiconductor memory device of  claim 11 , wherein the memory hole is a rectangular hole and a plurality of discrete memory layer stacks are formed on one or more sidewalls of the memory hole. 
     
     
         18 . The 3D semiconductor memory device of  claim 17 , wherein the plurality of discrete memory layer stacks are formed on opposing sidewalls of the memory hole.