Low Parasitic Capacitance RF Transistors

Abstract

Structures and fabrication methods for transistors having low parasitic capacitance, the transistors including an insulating low dielectric constant first or second handle wafer. In one embodiment, a Single Layer Transfer technique is used to position an insulating LDC handle wafer proximate the metal interconnect layers of an SOI transistor/metal layer stack in lieu of the silicon substrate of conventional designs. In another embodiment, a Double Layer Transfer technique is used to replace the silicon substrate of prior art structures with an insulating LDC substrate. In some embodiments, the insulating LDC handle wafer includes at least one air cavity, which reduces the effective dielectric constant of material surrounding an RF FET. An insulating LDC handle wafer reduces insertion loss and non-linearity, increases isolation, provides for more ideal voltage division of stacked transistors, enables a higher Q factor due to lower coupling losses, and otherwise mitigates various parasitic effects.

1 . A semiconductor structure comprising a silicon active layer having a first and a second surface; a first insulating layer proximate a portion of the first surface of the silicon active layer; a second insulating layer proximate a portion of the second surface of the silicon active layer; at least one patterned metal interconnect layer proximate the second insulating layer; a third insulating layer proximate the at least one patterned metal interconnect layer; and an insulating low dielectric constant substrate proximate the third insulating layer. 
     
     
         2 . The invention of  claim 1 , further including a redistribution layer proximate the first insulating layer. 
     
     
         3 . The invention of  claim 1 , further including a MOSFET having a source, a body, a gate, and a drain formed in and/or on the silicon active layer. 
     
     
         4 . The invention of  claim 3 , further including a CAS gate proximate the first insulating layer and the MOSFET body. 
     
     
         5 . The invention of  claim 3 , further including a thermal conduction structure for the MOSFET that includes:
 (a) at least one laterally-extending thermal path having a near portion in close thermal contact with the MOSFET, and a far portion sufficiently spaced away from the MOSFET in a lateral direction from the MOSFET so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the MOSFET; and   (b) at least one generally orthogonal thermal pathway thermally coupled to the at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one externally accessible thermal pad.   
     
     
         6 . (canceled) 
     
     
         7 . The invention of  claim 1 , wherein the insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high temperature co-fired ceramic (HTCC), or low temperature co-fired ceramic (LTCC). 
     
     
         8 . The invention of  claim 1 , wherein the insulating low dielectric constant substrate has a dielectric constant less than the dielectric constant of silicon. 
     
     
         9 . The invention of  claim 1 , wherein the insulating low dielectric constant substrate has a dielectric constant no greater than about 10.8. 
     
     
         10 . (canceled) 
     
     
         11 . The invention of  claim 1 , wherein the insulating low dielectric constant substrate includes at least one air cavity formed proximate the at least one patterned metal interconnect layer. 
     
     
         12 . A semiconductor structure comprising a silicon active layer having a first and a second surface; a first insulating layer proximate a portion of the first surface of the silicon active layer; a second insulating layer proximate a portion of the second surface of the silicon active layer; at least one patterned metal interconnect layer proximate the second insulating layer; a third insulating layer proximate the first insulating layer; and an insulating low dielectric constant substrate proximate the third insulating layer. 
     
     
         13 . The invention of  claim 12 , further including a redistribution layer proximate the first insulating layer. 
     
     
         14 . The invention of  claim 12 , further including a MOSFET having a source, a body, a gate, and a drain formed in and/or on the silicon active layer. 
     
     
         15 . The invention of  claim 14 , further including a CAS gate proximate the first insulating layer and the MOSFET body. 
     
     
         16 . The invention of  claim 14 , further including a thermal conduction structure for the MOSFET that includes:
 (a) at least one laterally-extending thermal path having a near portion in close thermal contact with the MOSFET, and a far portion sufficiently spaced away from the MOSFET in a lateral direction from the MOSFET so as to be couplable to a generally orthogonal thermal pathway, each laterally-extending thermal path being substantially electrically isolated from the MOSFET; and   (b) at least one generally orthogonal thermal pathway thermally coupled to at least one laterally-extending thermal path and configured to convey heat from the at least one laterally-extending thermal path to at least one externally accessible thermal pad.   
     
     
         17 . (canceled) 
     
     
         18 . The invention of  claim 14 , further including at least one air cavity formed in the insulating low dielectric constant substrate proximate the MOSFET. 
     
     
         19 . The invention of  claim 12 , wherein the insulating low dielectric constant substrate is one of the following: glass, quartz, fused silica, sapphire, aluminum nitride, silicon carbide, high temperature co-fired ceramic (HTCC), or low temperature co-fired ceramic (LTCC). 
     
     
         20 . The invention of  claim 12 , wherein the insulating low dielectric constant substrate has a dielectric constant less than the dielectric constant of silicon. 
     
     
         21 . The invention of  claim 12 , wherein the insulating low dielectric constant substrate has a dielectric constant no greater than about 10.8. 
     
     
         22 . (canceled) 
     
     
         23 . A semiconductor structure comprising a stack of formed layers, including, in relative order:
 (a) an insulating low dielectric constant substrate;   (b) at least one metal interconnect layer embedded in insulating dielectric material;   (c) a silicon active layer including at least one field effect transistor;   (d) a buried oxide layer; and   (e) an insulating dielectric material layer.   
     
     
         24 . A semiconductor structure comprising a stack of formed layers, including, in relative order:
 (a) an insulating low dielectric constant substrate;   (b) an insulating dielectric material layer;   (c) a buried oxide layer;   (d) a silicon active layer including at least one field effect transistor;   (e) at least one metal interconnect layer embedded in insulating dielectric material; and   (f) a passivation layer.   
     
     
         25 .- 46 . (canceled)