Vertical stacks of light emitting diodes and control transistors and method of making thereof

Abstract

A light emitting device includes a vertical stack of a light emitting diode and a field effect transistor that controls the light emitting diode. An isolation layer is present between the light emitting diode and the field effect transistor, and an electrically conductive path electrically shorts a node of the light emitting diode to a node of the field effect transistor. The field effect transistor may include an indium gallium zinc oxide (IGZO) channel and may be located over the isolation layer. Alternatively, the field effect transistor may be a high-electron-mobility transistor (HEMT) including an epitaxial semiconductor channel layer and the light emitting diode may be located over the HEMT.

What is claimed is: 
     
         1 . A light emitting device, comprising:
 an epitaxial substrate;   a light emitting diode comprising an n-doped semiconductor material layer, a light-emitting active region, and a p-doped semiconductor material layer, wherein the light-emitting active region comprises an epitaxial semiconductor material in epitaxial alignment with the epitaxial substrate;   at least one dielectric isolation layer overlying the light emitting diode;   a field effect transistor located over the dielectric isolation layer and comprising an indium gallium zinc oxide (IGZO) channel; and   an electrically conductive path that electrically shorts a node of the light emitting diode to a node of the field effect transistor.   
     
     
         2 . The light emitting device of  claim 1 , wherein the electrically conductive path comprises a contact via structure that extends through the at least one dielectric isolation layer. 
     
     
         3 . The light emitting device of  claim 2 , wherein the electrically conductive path further comprises a conductive line structure that contacts a top surface of the contact via structure and located over the field effect transistor. 
     
     
         4 . The light emitting device of  claim 2 , wherein the light emitting diode comprises a top electrode contacting a top surface of the p-doped semiconductor material layer and contacting a bottom surface of the contact via structure. 
     
     
         5 . The light emitting device of  claim 1 , wherein the node of the field effect transistor comprises a source region or a drain region of the field effect transistor. 
     
     
         6 . The light emitting device of  claim 1 , wherein:
 the IGZO channel is located above a top surface of the at least one dielectric isolation layer;   the field effect transistor comprises a gate dielectric contacting a top surface of the IGZO channel; and   a gate electrode of the field effect transistor overlies the gate dielectric.   
     
     
         7 . The light emitting device of  claim 1 , wherein:
 a gate electrode of the field effect transistor is embedded within a top portion of, or located over, the at least one dielectric isolation layer;   a gate dielectric of the field effect transistor overlies the gate electrode and the at least one dielectric isolation layer; and   the IGZO channel is located above a top surface of the gate dielectric.   
     
     
         8 . A light emitting device, comprising:
 an epitaxial substrate;   a high-electron-mobility transistor (HEMT) located on the epitaxial substrate and comprising an epitaxial semiconductor channel layer;   at least one isolation layer located over the HEMT;   a light emitting diode comprising an n-doped semiconductor material layer, a light-emitting active region, and a p-doped semiconductor material layer, wherein the light-emitting active region comprises an epitaxial semiconductor material in epitaxial alignment with the at least one isolation layer; and   an electrically conductive path that electrically shorts a node of the light emitting diode to a node of the HEMT.   
     
     
         9 . The light emitting device of  claim 8 , wherein the electrically conductive path comprises a contact via structure that extends through the at least one isolation layer. 
     
     
         10 . The light emitting device of  claim 9 , wherein the electrically conductive path further comprises a conductive line structure that is located above a top surface of the at least one isolation layer and contacts a top surface of the contact via structure. 
     
     
         11 . The light emitting device of  claim 9 , wherein a bottom surface of the contact via structure contacts a source electrode of the HEMT or a drain electrode of the HEMT. 
     
     
         12 . The light emitting device of  claim 9 , further comprising a dielectric liner laterally surrounding the conductive via structure and extending through each of the at least one isolation layer. 
     
     
         13 . The light emitting device of  claim 8 , wherein the at least one isolation layer comprises an epitaxial dielectric material in epitaxial alignment with the epitaxial semiconductor channel layer. 
     
     
         14 . The light emitting device of  claim 13 , wherein the at least one isolation layer comprises a layer stack including, from bottom to top:
 a first graded aluminum gallium nitride layer in which an atomic concentration of aluminum increases with a vertical distance from the epitaxial substrate;   an aluminum nitride layer located on the first graded aluminum gallium nitride layer and including aluminum nitride as the epitaxial dielectric material; and   a second graded aluminum gallium nitride layer in which an atomic concentration of aluminum increases with a vertical distance from the epitaxial substrate.   
     
     
         15 . A method of forming a light emitting device, comprising:
 forming a light emitting diode comprising an n-doped semiconductor material layer, a light-emitting active region, and a p-doped semiconductor material layer over an epitaxial substrate, wherein the light-emitting active region comprises an epitaxial semiconductor material in epitaxial alignment with the epitaxial substrate;   forming at least one dielectric isolation layer over the light emitting diode;   forming a field effect transistor comprising an indium gallium zinc oxide (IGZO) channel over the dielectric isolation layer; and   forming an electrically conductive path that electrically shorts a node of the light emitting diode to a node of the field effect transistor.   
     
     
         16 . The method of  claim 15 , wherein forming the electrically conductive path comprises forming a contact via structure through the at least one dielectric isolation layer. 
     
     
         17 . The method of  claim 15 , wherein:
 the IGZO channel is formed on a top surface of the at least one dielectric isolation layer by deposition and patterning of an IGZO layer; and   forming the field effect transistor comprises:
 forming a gate dielectric of the field effect transistor on a top surface of the IGZO channel; and 
 forming a gate electrode of the field effect transistor over the gate dielectric. 
   
     
     
         18 . The method of  claim 15 , wherein forming the field effect transistor comprises:
 forming a gate electrode of the field effect transistor within a top portion of, or over, the at least one dielectric isolation layer;   forming a gate dielectric of the field effect transistor over the gate electrode and the at least one dielectric isolation layer; and   forming the IGZO channel on a top surface of the gate dielectric.   
     
     
         19 . A method of forming a light emitting device, comprising:
 forming a high-electron-mobility transistor (HEMT) comprising an epitaxial semiconductor channel layer and on an epitaxial substrate;   forming at least one isolation layer over the HEMT, wherein the at least one epitaxial dielectric isolation layer comprises an epitaxial dielectric material in epitaxial alignment with the epitaxial semiconductor channel layer;   forming a light emitting diode comprising an n-doped semiconductor material layer, a light-emitting active region, and a p-doped semiconductor material layer over the at least one epitaxial dielectric isolation layer, wherein the light-emitting active region comprises an epitaxial semiconductor material in epitaxial alignment with the at least one epitaxial dielectric isolation layer; and   forming an electrically conductive path comprising a contact via structure that extends through the at least one epitaxial dielectric isolation layer, wherein the electrically conductive path electrically shorts a node of the light emitting diode to a node of the HEMT.   
     
     
         20 . The method of  claim 19 , wherein forming the electrically conductive path comprises forming a contact via structure through the at least one dielectric isolation layer. 
     
     
         21 . The method of  claim 19 , wherein forming the at least one dielectric isolation layer comprises epitaxially growing an epitaxial dielectric material in epitaxial alignment with the epitaxial semiconductor channel layer. 
     
     
         22 . The method of  claim 21 , wherein forming the at least one dielectric isolation layer comprises:
 forming a first graded aluminum gallium nitride layer in which an atomic concentration of aluminum increases with a vertical distance from the epitaxial substrate on the HEMT;   forming an aluminum nitride layer including aluminum nitride as the epitaxial dielectric material on the first graded aluminum gallium nitride layer; and   forming a second graded aluminum gallium nitride layer in which an atomic concentration of aluminum increases with a vertical distance from the epitaxial substrate on the aluminum nitride layer.