Semiconductor Fin Length Variability Control

Abstract

Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

What is claimed is: 
     
         1 . A device, comprising:
 fins patterned in a wafer, wherein the fins have a uniform length L;   a gate disposed over a portion of the fins that serves as a channel region of the device;   source and drain regions disposed over portions of the fins extending out from under the gate; and   spacers offsetting the gate from the source and drains.   
     
     
         2 . The device of  claim 1 , wherein the uniform length L varies by less than about 2% from fin-to-fin. 
     
     
         3 . The device of  claim 1 , wherein the fins have a width of from about 10 nm to about 20 nm and ranges therebetween. 
     
     
         4 . The device of  claim 1 , wherein the fins have a width of from about 2 nm to about 15 nm and ranges therebetween. 
     
     
         5 . The device of  claim 1 , wherein the wafer is a bulk semiconductor wafer. 
     
     
         6 . The device of  claim 5 , wherein the bulk semiconductor wafer is selected from the group consisting of: a bulk silicon (Si) wafer, a bulk germanium (Ge) wafer, a bulk silicon germanium (SiGe) wafer, a bulk III-V semiconductor wafer, and combinations thereof. 
     
     
         7 . The device of  claim 1 , wherein the wafer is a semiconductor-on-insulator (SOI) wafer. 
     
     
         8 . The device of  claim 7 , wherein the SOI wafer comprises an SOI layer comprising a semiconductor selected from the group consisting of: Si, Ge, SiGe, a III-V semiconductor, and combinations thereof. 
     
     
         9 . The device of  claim 1 , wherein the device comprises a fin field-effect transistor (finFET) device. 
     
     
         10 . A finFET device, comprising:
 fins patterned in a wafer, wherein the fins have a uniform length L that varies by less than about 2% from fin-to-fin;   a gate disposed over a portion of the fins that serves as a channel region of the device;   source and drain regions disposed over portions of the fins extending out from under the gate; and   spacers offsetting the gate from the source and drains.   
     
     
         11 . The finFET device of  claim 10 , wherein the fins have a width of from about 10 nm to about 20 nm and ranges therebetween. 
     
     
         12 . The finFET device of  claim 10 , wherein the fins have a width of from about 2 nm to about 15 nm and ranges therebetween. 
     
     
         13 . The finFET device of  claim 10 , wherein the wafer is a bulk semiconductor wafer. 
     
     
         14 . The finFET device of  claim 13 , wherein the bulk semiconductor wafer is selected from the group consisting of: a bulk Si wafer, a bulk Ge wafer, a bulk SiGe wafer, a bulk III-V semiconductor wafer, and combinations thereof. 
     
     
         15 . The finFET device of  claim 10 , wherein the wafer is an SOI wafer. 
     
     
         16 . The finFET device of  claim 15 , wherein the SOI wafer comprises an SOI layer comprising a semiconductor selected from the group consisting of: Si, Ge, SiGe, a III-V semiconductor, and combinations thereof. 
     
     
         17 . A finFET device, comprising:
 fins patterned in a wafer, wherein the fins have a uniform length L that varies by less than about 2% from fin-to-fin, and wherein the fins have a width of from about 10 nm to about 20 nm and ranges therebetween;   a gate disposed over a portion of the fins that serves as a channel region of the device;   source and drain regions disposed over portions of the fins extending out from under the gate; and   spacers offsetting the gate from the source and drains.   
     
     
         18 . The finFET device of  claim 17 , wherein the fins have a width of from about 2 nm to about 15 nm and ranges therebetween. 
     
     
         19 . The finFET device of  claim 17 , wherein the wafer is a bulk semiconductor wafer selected from the group consisting of: a bulk Si wafer, a bulk Ge wafer, a bulk SiGe wafer, a bulk III-V semiconductor wafer, and combinations thereof. 
     
     
         20 . The finFET device of  claim 17 , wherein the wafer is an SOI wafer comprising an SOI layer comprising a semiconductor selected from the group consisting of: Si, Ge, SiGe, a III-V semiconductor, and combinations thereof.