Flash memories and methods for manufacturing the same

Abstract

A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

What is claimed is: 
     
         1 . A flash memory, comprising:
 a floating gate disposed on a semiconductor substrate, wherein a first edge of the floating gate is a first sharp tip, and a second edge of the floating gate is a second sharp tip;   an oxide structure disposed on the floating gate, wherein a first protruding portion of the oxide structure is located directly above the first sharp tip, and a second protruding portion of the oxide structure is located directly above the second sharp tip; and   a source region and a drain region disposed in the semiconductor substrate, and the floating gate is located between the source region and the drain region.   
     
     
         2 . The flash memory as claimed in  claim 1 , wherein the floating gate has a thickness that decreases gradually from the first edge and the second edge toward a middle portion of the floating gate, such that the floating gate has a concave top surface. 
     
     
         3 . The flash memory as claimed in  claim 1 , wherein the first protruding portion and the second protruding portion of the oxide structure have rounded top surfaces. 
     
     
         4 . The flash memory as claimed in  claim 1 , wherein the oxide structure has a flat top surface between the first protruding portion and the second protruding portion. 
     
     
         5 . The flash memory as claimed in  claim 1 , further comprising:
 a dielectric layer covering a sidewall of the floating gate; and   a control gate disposed on the semiconductor substrate, wherein the control gate extends onto the first protruding portion of the oxide structure.   
     
     
         6 . The flash memory as claimed in  claim 5 , wherein the floating gate and the control gate are made of polysilicon. 
     
     
         7 . The flash memory as claimed in  claim 5 , wherein the control gate is separated from the floating gate by the dielectric layer, and the second protruding portion of the oxide structure is not covered by the control gate.