Integrated circuits with memory cells and methods for producing the same

Abstract

Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a lower contact in a lower interlayer dielectric layer. A base contact layer is formed overlying the lower interlayer dielectric layer and the lower contact, and a base contact is formed by removing a portion of the base contact layer. The base contact is formed in electrical communication with the lower contact. A base interlayer dielectric layer is formed overlying the lower interlayer dielectric layer after forming the base contact, where the base interlayer dielectric layer is adjacent to a base contact side surface. A memory cell is formed overlying the base contact, where the memory cell is in electrical communication with the base contact.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a base interlayer dielectric layer;   a base contact extending through the base interlayer dielectric layer, wherein the base contact has a base contact top surface area; and   a memory cell overlying the base contact, wherein the memory cell is in electrical communication with the base contact, wherein the memory cell has a memory cell bottom surface area that is greater than the base contact top surface area.   
     
     
         2 . The integrated circuit of  claim 1  further comprising:
 an exposed base contact top surface area. 
 
     
     
         3 . The integrated circuit of  claim 1  further comprising:
 a base contact photoresist layer over the base contact. 
 
     
     
         4 . The integrated circuit of  claim 1  wherein:
 the base contact layer includes an electrically conductive material; 
 the base contact includes an electrical conductor; and 
 the base interlayer dielectric layer includes an electrical insulator. 
 
     
     
         5 . The integrated circuit of  claim 1  wherein:
 the memory cell is a magnetic tunnel junction memory cell. 
 
     
     
         6 . The integrated circuit of  claim 1  wherein:
 the base contact layer comprises an element with an atomic number selected from the group of 22 to 33, 40 to 52, 57 to 85, 88 to 117, or a combination thereof. 
 
     
     
         7 . The integrated circuit of  claim 1  wherein:
 the base contact layer comprises an element with an atomic number of from 72 to 85, or a combination thereof. 
 
     
     
         8 . The integrated circuit of  claim 1  wherein the base contact layer comprises tantalum nitride. 
     
     
         9 . The integrated circuit of  claim 1  wherein:
 the base contact is free of a void. 
 
     
     
         10 . The integrated circuit of  claim 1  further comprising:
 an alignment mark trench in the lower interlayer dielectric layer; and 
 a portion of the base contact layer within the alignment mark trench. 
 
     
     
         11 . The integrated circuit of  claim 1  wherein:
 the memory cell is in direct contact with the base contact. 
 
     
     
         12 . The integrated circuit of  claim 1  wherein:
 the memory cell includes a memory cell bottom surface area, and wherein the memory cell bottom surface area is greater than the base contact top surface area. 
 
     
     
         13 . The integrated circuit of  claim 1  wherein the base interlayer dielectric layer is in direct contact with the base contact side surface. 
     
     
         14 . The integrated circuit of  claim 1  wherein:
 a portion of the lower contact is exposed. 
 
     
     
         15 . An integrated circuit comprising:
 a lower contact in a lower interlayer dielectric layer   a base contact layer overlying the lower interlayer dielectric layer and the lower contact;   a base contact formed by removing a portion of the base contact layer, wherein the base contact is in electrical communication with the lower contact, and wherein the base contact has a base contact top surface area; and   a memory cell formed directly overlying the base contact, wherein the memory cell includes a memory cell bottom surface area that is greater than the base contact top surface area, and wherein the memory cell is in electrical communication with the base contact.   
     
     
         16 . The integrated circuit of  claim 15  further comprising:
 an alignment mark trench in the lower interlayer dielectric layer; and 
 wherein the base contact layer is removed from within the alignment mark trench. 
 
     
     
         17 . The integrated circuit of  claim 15  further comprising:
 the base interlayer dielectric layer directly contacts a base contact side surface. 
 
     
     
         18 . The integrated circuit of  claim 15  wherein:
 the base contact is free of a void. 
 
     
     
         19 . An integrated circuit comprising:
 a base interlayer dielectric layer including a portion of the interlayer dielectric layer exposed through a block layer;   a base contact extending through the base interlayer dielectric layer, wherein the base contact has a base contact top surface area and wherein a base contact bottom surface covers the exposed portion of the interlayer dielectric layer; and   a memory cell overlying the base contact, wherein the memory cell is in electrical communication with the base contact, wherein the memory cell has a memory cell bottom surface area that is greater than the base contact top surface area.   
     
     
         20 . The integrated circuit of  claim 19  wherein:
 a base contact photoresist layer over the base contact.