High Electron Mobility Transistor and Method for Manufacturing the Same

Abstract

The present disclosure provides a high electron mobility transistor, including a silicon substrate, a channel layer, a barrier layer and a gate sequentially stacked in a thickness direction of the high electron mobility transistor. The high electron mobility transistor further includes a strain layer made of an insulating material. A surface of the barrier layer distal to the channel layer includes a gate region and an enhancement region. The gate is disposed in the gate region. The strain layer includes an enhancement portion stacked in the enhancement region. A mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%. The present disclosure further provides a method for manufacturing a high electron mobility transistor. The high electron mobility transistor has good performance and low cost.

1 . A high electron mobility transistor, comprising:
 a silicon substrate, a channel layer, a barrier layer, and a gate; with the silicon substrate, the channel layer, the barrier layer, and the gate being sequentially stacked in a thickness direction of the high electron mobility transistor;   wherein the high electron mobility transistor further comprises a strain layer made of an insulating material, a surface of the barrier layer distal to the channel layer comprises a gate region and an enhancement region, the gate is disposed in the gate region, the strain layer comprises an enhancement portion stacked in the enhancement region, and a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.   
     
     
         2 . The high electron mobility transistor of  claim 1 , wherein the strain layer further comprises a gate covering portion covering an outer surface of the gate, and the gate covering portion and the enhancement portion are formed as a whole. 
     
     
         3 . The high electron mobility transistor of  claim 1 , wherein a material of the strain layer comprises a nitrogen-based material and/or an oxygen-based material. 
     
     
         4 . The high electron mobility transistor of  claim 3 , wherein the material of the strain layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride. 
     
     
         5 . The high electron mobility transistor of  claim 3 , wherein a thickness of the strain layer is between 1 nm and 100 nm. 
     
     
         6 . The high electron mobility transistor of  claim 1 , further comprising a source, a drain, a passivation layer stacked on the strain layer, and a planarization layer stacked on a surface of the passivation layer,
 wherein the source is connected to the barrier layer through a source via hole penetrating through the planarization layer, the passivation layer and the strain layer, and the drain is connected to the barrier layer through a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer.   
     
     
         7 . The high electron mobility transistor of  claim 1 , further comprising a buffer layer disposed between the silicon substrate and the channel layer. 
     
     
         8 . The high electron mobility transistor of  claim 1 , wherein a material of the channel layer comprises GaN, and a material of the barrier layer comprises AlGaN. 
     
     
         9 . A method for manufacturing a high electron mobility transistor, comprising:
 providing a silicon substrate;   forming a channel layer;   forming a barrier layer, a surface of the barrier layer distal to the channel layer comprising a gate region and an enhancement region;   forming a gate in the gate region; and   forming a strain layer using an insulating material, the strain layer comprising an enhancement portion disposed in the enhancement region, wherein a mismatch rate of a lattice constant of the strain layer to a lattice constant of the barrier layer is not less than 0.5%.   
     
     
         10 . The method of  claim 9 , wherein the strain layer further comprises a gate covering portion covering an outer surface of the gate, the gate covering portion and the enhancement portion being formed as a whole. 
     
     
         11 . The method of  claim 9 , wherein a material of the strain layer comprises a nitrogen-based material and/or an oxygen-based material. 
     
     
         12 . The method of  claim 11 , wherein the material of the strain layer comprises at least one of silicon nitride, silicon oxide, silicon oxynitride, boron oxide, boron nitride, boron oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, titanium oxide, titanium nitride, and titanium oxynitride. 
     
     
         13 . The method of  claim 11 , wherein a thickness of the strain layer is between 1 nm and 100 nm. 
     
     
         14 . The method of  claim 9 , further comprising, after the step of forming the strain layer, steps of:
 forming a passivation layer;   forming a planarization layer;   forming a source via hole penetrating through the planarization layer, the passivation layer and the strain layer and a drain via hole penetrating through the planarization layer, the passivation layer and the strain layer; and   forming a source and a drain, wherein the source is connected to the barrier layer through the source via hole, and the drain is connected to the barrier layer through the drain via hole.   
     
     
         15 . The method of  claim 9 , further comprising, between the step of providing the silicon substrate and the step of forming the channel layer, a step of:
 forming a buffer layer.   
     
     
         16 . The method of  claim 9 , wherein a material of the channel layer comprises GaN, and a material of the barrier layer comprises AlGaN.