Branch type logging in last branch registers

Abstract

A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

What is claimed is: 
     
         1 . A processor, comprising:
 a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions; and   a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information comprising:
 a first value of the counter when the first branch instruction is retired; 
 a second value of the counter when the second branch instruction is retired; 
 a first type information value indicating a type of the first branch instruction; and 
 a second type information value indicating a type of the second branch instruction. 
   
     
     
         2 . The processor of  claim 1 , wherein the stack of registers is a stack of last branch record (LBR) registers, and the branch type information is LBR information. 
     
     
         3 . The processor of  claim 1 , wherein the first type information value is to indicate one of a conditional instruction, an indirect jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction. 
     
     
         4 . The processor of  claim 1 , wherein the second type information value is to indicate one of a conditional instruction, an unconditional instruction, an indirect jump instruction, a direct jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction. 
     
     
         5 . The processor of  claim 1 , wherein the stack of registers is further to store branch type information comprising a misprediction value that indicates whether at least one of the first branch instruction or the second branch instruction has been mispredicted. 
     
     
         6 . The processor of  claim 1 , wherein the stack of registers is further to store branch type information comprising a transaction value that indicates whether at least one of the first branch instruction or the second branch instruction is in a transactional region of the set of instructions. 
     
     
         7 . The processor of  claim 1 , wherein the stack of registers is further to store branch type information comprising an abort value that indicates whether at least one of the first branch instruction or the second branch instruction has been aborted. 
     
     
         8 . The processor of  claim 1 , further comprising an execution engine circuit that comprises the stack of registers, the execution engine circuit to:
 analyze the branch type information; and   construct a control flow sequence indicating an order in which individual statements, instructions, and function calls have been executed as part of a program comprising the set of instructions.   
     
     
         9 . A system comprising:
 a memory to store a set of instructions, the set of instructions comprising a first branch instruction and a second branch instruction; and   a processor coupled to the memory, the processor comprising:
 a counter to store a value that indicates a cycle count of the processor; and 
 an execution engine circuit comprising a stack of registers, wherein the stack of registers is to store branch type information comprising:
 a first value of the counter when the first branch instruction is retired; 
 a second value of the counter when the second branch instruction is retired; 
 a first type information value indicating a type of the first branch instruction; and 
 a second type information value indicating a type of the second branch instruction. 
 
   
     
     
         10 . The system of  claim 9 , wherein the stack of registers is a stack of last branch record (LBR) registers, and the branch type information is LBR information. 
     
     
         11 . The system of  claim 9 , wherein the second type information value is to indicate one of a conditional instruction, an indirect jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction. 
     
     
         12 . The system of  claim 9 , wherein the first type information value is to indicate one of a conditional instruction, an unconditional instruction, an indirect jump instruction, a direct jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction. 
     
     
         13 . The system of  claim 9 , wherein the stack of registers is further to store branch type information comprising a misprediction value that indicates whether at least one of the first branch instruction or the second branch instruction has been mispredicted. 
     
     
         14 . The system of  claim 9 , wherein the stack of registers is further to store branch type information comprising a transaction value that indicates whether at least one of the first branch instruction or the second branch instruction is in a transactional region of the set of instructions. 
     
     
         15 . The system of  claim 9 , wherein the stack of registers is further to store branch type information comprising an abort value that indicates whether at least one of the first branch instruction or the second branch instruction has been aborted. 
     
     
         16 . The system of  claim 9 , wherein the execution engine circuit to:
 analyze the branch type information; and   construct a control flow sequence indicating an order in which individual statements, instructions, and function calls have been executed as part of a program comprising the set of instructions.   
     
     
         17 . A method comprising:
 retiring, by a processor, a first branch instruction of a set of instructions;   storing, by the processor in a stack of registers, a first value of a counter that indicates a first cycle count of the processor when the first branch instruction retired;   storing, by the processor in the stack of registers, a first type information value indicating a type of the first branch instruction;   retiring, by the processor, a second branch instruction for the set of instructions;   storing, by the processor in the stack of registers, a second value of the counter that indicates a second cycle count of the processor when the second branch instruction retired; and   storing, by the processor in the stack of registers, a second type information value indicating a type of the first branch instruction.   
     
     
         18 . The method of  claim 17 , wherein one of the first type information value or the second type information value is to indicate one of a conditional instruction, an unconditional instruction, an indirect jump instruction, a direct jump instruction, a direct call instruction, an indirect call instruction, a return instruction, or a far instruction. 
     
     
         19 . The method of  claim 17 , further comprising storing, in the stack of registers, branch type information comprising at least one of:
 a misprediction value that indicates whether one of the first branch instruction or the second branch instruction has been mispredicted;   a transaction value that indicates whether one of the first branch instruction or the second branch instruction is in a transactional region of the set of instructions; or   an abort value that indicates whether one of the first branch instruction or the second branch instruction has been aborted.   
     
     
         20 . The method of  claim 17 , further comprising:
 analyzing, by the processor, the branch type information; and   constructing, by the processor, a control flow sequence indicating an order in which individual statements, instructions, and function calls have been executed as part of a program comprising the set of instructions.