Thread Scheduling Using Processing Engine Information

Abstract

In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

1 . A processor comprising:
 a plurality of cores to process instructions of a plurality of threads;   execution circuitry of at least one core of the plurality of cores to execute a plurality of the instructions; and   core prioritization hardware logic to generate core prioritization data for a scheduler, the core prioritization data generated based on a combination of: (a) measured properties of the plurality of cores independent of thread characteristics, including maximum clock rates of the plurality of cores, (b) data related to thermal management of the processor, and (c) execution characteristics associated with a thread,   wherein the core prioritization hardware logic provides the core prioritization data for use by a scheduler to identify a first core.   
     
     
         2 . The processor of  claim 1  wherein the measured properties of the plurality of cores comprise thread-agnostic performance rankings comprising a first prioritized ordering of the plurality of cores generated based on thread-agnostic performance data. 
     
     
         3 . The processor of  claim 1  wherein the scheduler comprises an operating system (OS) scheduler. 
     
     
         4 . The processor of  claim 3  further comprising:
 a hardware-OS interface comprising a plurality of registers coupled to the core prioritization hardware logic, the OS scheduler to read at least a portion of the prioritization data from the plurality of registers. 
 
     
     
         5 . The processor of  claim 1  further comprising:
 power control circuitry to control power consumed by the plurality of cores, the power control circuitry to cause a core of the plurality of cores to operate at a different frequency and/or voltage than one or more other cores of the plurality of cores; and 
 a hardware monitor to monitor execution of the plurality of threads on the plurality of cores to generate at least a portion of the thermal management data associated with the processor and/or the execution characteristics associated with a thread. 
 
     
     
         6 . The processor of  claim 5  wherein the power control circuitry is to implement dynamic voltage and frequency scaling (DVFS) to cause the core of the plurality of cores to operate at a different frequency and/or voltage than one or more other cores of the plurality of cores. 
     
     
         7 . The processor of  claim 6  wherein the power control circuitry comprises a microcontroller to execute dedicated power management code.