Multilayers of nickel alloys as diffusion barrier layers

Abstract

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1<a2. The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.

What is claimed is: 
     
         1 . An integrated circuit package comprising:
 a die; and   a bump electrically connected to the die, the bump comprising:
 a copper (Cu) layer; 
 a nickel alloy layer over the copper layer, the nickel alloy layer including an element from a lanthanoid group; and 
 a tin (Sn) layer formed over the nickel alloy layer. 
   
     
     
         2 . The integrated circuit package of  claim 1 , wherein the copper layer is over a pad of the die. 
     
     
         3 . The integrated circuit package of  claim 1 , wherein the nickel alloy layer includes one of NiCe, NiMoW, and NiWCe. 
     
     
         4 . The integrated circuit package of  claim 1 , wherein the nickel alloy layer includes a first nickel alloy layer and a second nickel alloy layer adjacent to each other. 
     
     
         5 . The integrated circuit package of  claim 4 , wherein the first nickel alloy layer includes a nickel grain size a 1 , and the second nickel alloy layer with a nickel grain size a 2 , wherein a 1 <a 2 . 
     
     
         6 . The integrated circuit package of  claim 5 , wherein some of the alloy in the first nickel alloy layer, and the second nickel alloy layer is solubilized in nickel, while the remainder of the alloy is at boundaries of the nickel grains in each of the nickel alloy layers. 
     
     
         7 . The integrated circuit package of  claim 1 , wherein the nickel alloy layer includes a first nickel alloy layer, a second nickel alloy layer, and a third nickel alloy layer adjacent to each other. 
     
     
         8 . The integrated circuit package of  claim 7 , wherein the first nickel alloy layer includes a nickel grain size a 1 , the second nickel alloy layer with a nickel grain size a 2 , and the third nickel alloy layer with a Ni grain size a 3 , wherein a 1 <a 2 <a 3 . 
     
     
         9 . The integrated circuit package of  claim 8 , wherein some of the alloy in the first nickel alloy layer, the second nickel alloy layer, and the third nickel alloy layer is solubilized in nickel, while the remainder of the alloy is at boundaries of the nickel grains in each of the nickel alloy layers. 
     
     
         10 . The integrated circuit package of  claim 1 , wherein the nickel barrier layer functions as a barrier layer to contain formation of intermetallic compounds between the copper layer and the tin layer. 
     
     
         11 . An integrated circuit package comprising:
 a die; and   a bump electrically connected to the die, the bump comprising:
 a copper (Cu) layer; 
 a nickel alloy layer over the copper layer, the nickel alloy layer including an element from one of molybdenum, lanthanoid, and cerium; and 
 a tin (Sn) layer formed over the nickel alloy layer. 
   
     
     
         12 . The integrated circuit package of  claim 11 , wherein the copper layer is over an aluminum pad of the die. 
     
     
         13 . The integrated circuit package of  claim 11 , wherein the nickel alloy layer includes a first nickel alloy layer and a second nickel alloy layer adjacent to each other. 
     
     
         14 . The integrated circuit package of  claim 13 , wherein the first nickel alloy layer includes a nickel grain size a 1 , and the second nickel alloy layer with a nickel grain size a 2 , wherein a 1 <a 2 . 
     
     
         15 . The integrated circuit package of  claim 14 , wherein some of the alloy in the first nickel alloy layer, and the second nickel alloy layer is solubilized in nickel, while the remainder of the alloy is at boundaries of the nickel grains in each of the nickel alloy layers. 
     
     
         16 . The integrated circuit package of  claim 11 , wherein the nickel alloy layer includes a first nickel alloy layer, a second nickel alloy layer, and a third nickel alloy layer adjacent to each other. 
     
     
         17 . The integrated circuit package of  claim 16 , wherein the first nickel alloy layer includes a nickel grain size a 1 , the second nickel alloy layer with a nickel grain size a 2 , and the third nickel alloy layer with a Ni grain size a 3 , wherein a 1 <a 2 <a 3 . 
     
     
         18 . The integrated circuit package of  claim 17 , wherein some of the alloy in the first nickel alloy layer, the second nickel alloy layer, and the third nickel alloy layer is solubilized in nickel, while the remainder of the alloy is at boundaries of the nickel grains in each of the nickel alloy layers. 
     
     
         19 . The integrated circuit package of  claim 11  further comprising an under bump metallization layer between the pad and the copper layer of the bump. 
     
     
         20 . An integrated circuit package comprising:
 a die;   a pad electrically connected to the die;   a metallization layer on the pad; and   a bump electrically connected to the metallization layer, the bump comprising:
 a copper (Cu) layer; 
 a nickel alloy layer over the copper layer, the nickel alloy layer including an element from a lanthanoid group; and 
 a tin (Sn) layer formed over the nickel alloy layer.