Transistors with dual wells

Abstract

In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.

1 . A transistor comprising:
 a substrate having a first conductivity type and a first dopant concentration;   a gate dielectric layer over a portion of the substrate and having first and second opposite sidewalls;   a gate electrode over the dielectric layer;   a first dielectric sidewall spacer on the first sidewall and a second dielectric sidewall spacer on the second sidewall;   a well having the first conductivity type and a second dopant concentration, the well underlapping first sidewall spacer;   a first source/drain region within the first well and having a second opposite conductivity type; and   a second source/drain region within the well and adjacent the second sidewall spacer, having the second conductivity type and having a third dopant concentration, the second source/drain region extending toward the first source/drain region no further than the second sidewall.   
     
     
         2 . The transistor of  claim 1 , wherein the well is a first well and further comprising a second well having the first conductivity type and spaced apart laterally from the first well, the second source/drain region located within the second well. 
     
     
         3 . The transistor of  claim 1 , wherein the second well underlaps the second sidewall spacer. 
     
     
         4 . The transistor of  claim 1 , wherein the second well does not underlap any portion of the gate electrode. 
     
     
         5 . The transistor of  claim 1 , wherein the second source/drain region touches the substrate. 
     
     
         6 . The transistor of  claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type . 
     
     
         7 . The transistor of  claim 1 , wherein the first-type dopant comprises elements from group V and the second-type dopant comprises elements from group III of the periodic table. 
     
     
         8 . The transistor of  claim 1 , wherein the second concentration is higher than the first concentration. 
     
     
         9 . The transistor of  claim 1  further comprising a corresponding silicide layer formed on each of the first source/drain region, the second source/drain region, and the gate layer electrode. 
     
     
         10 . An integrated circuit, comprising:
 first and second doped regions having a first conductivity type in a semiconductor substrate region having the first conductivity type, the first and second doped regions having a higher dopant concentration than the semiconductor substrate region, the second doped region being laterally offset from the first doped region, and an intervening region of the semiconductor substrate region being located between the first and second doped regions;   a third doped region and first extension both having a second opposite conductivity type within the first doped region, and a fourth doped region and a second extension both having the second conductivity type within the second doped region, the first and second extensions being located between and having a lower dopant concentration than the third and fourth doped regions, the third doped region and the first extension being isolated from the substrate region by the first doped region, and the fourth doped region and the second extension being isolated from the substrate region by the second doped region;   a dielectric layer directly on the intervening region;   a conductive structure between the third and fourth doped regions, directly on the dielectric layer, and over at least one of the first and second doped regions, the conductive structure having a first sidewall and a second opposing sidewall; and   a silicide layer over the third and fourth doped regions,   wherein the first extension extends from the third doped region toward the conductive structure no further than the first sidewall, and the second extension extends from the fourth doped region toward the conductive structure no further than the second sidewall.   
     
     
         11 . The integrated circuit of  claim 10 , wherein the conductive structure overlaps both the first and the second doped regions. 
     
     
         12 . The integrated circuit of  claim 10 , wherein the conductive structure overlaps only one of the first and the second doped regions. 
     
     
         13 . The integrated circuit of  claim 10 , wherein the third doped region is configured to operate as a source of a MOSFET, the fourth doped region is configured to operate as a drain of the MOSFET, and the conductive structure is configured to operate as a gate electrode of the MOSFET. 
     
     
         14 . The integrated circuit of  claim 10 , wherein the first conductivity type is p-type and the second conductivity type is n-type. 
     
     
         15 . The integrated circuit of  claim 10 , further comprising first and second dielectric structures on opposing sidewalls of the conductive structure, the first dielectric structure located over the first extension, and the second dielectric structure located over the second extension. 
     
     
         16 . The integrated circuit of  claim 10 , wherein the third and fourth doped regions have a higher dopant concentration than the first and second doped regions. 
     
     
         17 . An integrated circuit, comprising:
 a first doped region having a first conductivity type in a semiconductor substrate region having the first conductivity type, the first doped region having a higher dopant concentration than the semiconductor substrate region;   a second doped region having a second different conductivity type within the first doped region, the second doped region including a first subregion having a higher dopant concentration and a second subregion having a lower dopant concentration, and the second doped region isolated from the substrate region by the first doped region;   a dielectric layer that touches the first doped region and the second doped region;   a conductive structure and a sidewall dielectric structure, the conductive structure touching the dielectric layer and overlapping the first doped region and a portion of the semiconductor substrate region that touches the dielectric layer, and the sidewall spacer overlapping the second subregion; and   a silicide layer over the second doped region,   wherein an interface between the second doped region and the first doped region intersects a top surface of the semiconductor substrate under the sidewall dielectric structure.   
     
     
         18 . The integrated circuit of  claim 17 , further comprising:
 a third doped region having the first conductivity type within the semiconductor substrate region; and   a fourth doped region having the second conductivity type within the third doped region,   wherein the portion of the semiconductor substrate region that touches the dielectric layer is located between the first and third doped regions.   
     
     
         19 . The integrated circuit of  claim 18 , wherein the second doped region has a higher dopant concentration than the first doped region and the fourth doped region has a higher dopant concentration than the third doped region. 
     
     
         20 . The integrated circuit of  claim 17 , further comprising a sidewall dielectric layer on the conductive structure over the second subregion.