Embedded sonos with triple gate oxide and manufacturing method of the same

Abstract

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

What is claimed is: 
     
         1 . A method, comprising:
 forming a dielectric stack, including a cap layer, overlying first and second regions of a substrate;   patterning the dielectric stack to form a non-volatile (NV) gate stack of a non-volatile memory (NVM) transistor in the first region while concurrently removing the dielectric stack in the second region;   performing a first oxidation process to form a first gate oxide layer overlying the second region;   removing the first gate oxide layer from second and third areas of the second region, but leaving the first gate oxide layer in a first area of the second region;   performing a second oxidation process to form a second gate oxide layer in the second region, to concurrently consume at least a portion of the cap layer to form a blocking oxide of the NVM transistor in the first region, and to increase a thickness of the first gate oxide layer in the first area; and   removing the second gate oxide layer in the third area of the second region.