Method of making a moisture barrier for metal insulator metal capacitors in integrated circuits

Abstract

A semiconductor die includes a substrate layer, one or more metal layers disposed over the substrate layer, and one or more polyimide layers disposed over the substrate. Each polyimide layer can have a trench that separates a first portion of the polyimide layer that is adjacent a metal layer from a second portion of the polyimide layer. The trench(es) can be formed by etching the polyimide layer(s). A topcoat insulation layer can be disposed over the polyimide layers, a portion of the topcoat insulation layer disposed over the trench(es) define a moat. The topcoat insulation layer is impervious to moisture and the moat inhibits moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion.

What is claimed is: 
     
         1 . A method of making a semiconductor die comprising:
 forming or providing a substrate layer;   forming or applying one or more metal layers over the substrate layer;   forming or applying one or more polymer interlevel dielectric layers over the substrate layer, at least a first portion of the one or more polymer interlevel dielectric layers being adjacent at least one of the one or more metal layers;   forming a trench in the one or more polymer interlevel dielectric layers to separate the first portion from a second portion of the one or more polymer interlevel dielectric layers; and   forming or applying a topcoat insulation layer over the one or more polymer interlevel dielectric layers, a portion of the topcoat insulation layer disposed over the trench in at least one of the polymer interlevel dielectric layers to define a moat, the topcoat insulation layer being impervious to moisture, the moat inhibiting moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion.   
     
     
         2 . The method of  claim 1  wherein the one or more polymer interlevel dielectric layers are one or more polyimide interlevel dielectric layers. 
     
     
         3 . The method of  claim 1  wherein the one or more polymer interlevel dielectric layers are two polymer interlevel dielectric layers. 
     
     
         4 . The method of  claim 3  wherein the trench is formed in each of the two polymer interlevel dielectric layers in a stepped manner relative to each other. 
     
     
         5 . The method of  claim 1  wherein forming the trench includes etching the one or more polymer interlevel dielectric layers to form the trench. 
     
     
         6 . The method of  claim 1  wherein the one or more metal layers are one or more electrodes of a capacitor. 
     
     
         7 . The method of  claim 1  further comprising forming or applying one or more insulation layers at least partially over at least one of the one or more metal layers. 
     
     
         8 . The method of  claim 1  wherein forming the trench includes tapering the trench toward the substrate layer. 
     
     
         9 . The method of  claim 1  wherein the moat is arranged around a capacitor of the semiconductor die. 
     
     
         10 . The method of  claim 1  wherein the moat is arranged around a plurality of electronic components on the semiconductor die. 
     
     
         11 . A method of making a radiofrequency module, the method comprising:
 forming or providing a printed circuit board that includes a substrate layer;   forming or providing a semiconductor die comprising (a) forming or providing a substrate layer, (b) forming or applying one or more metal layers over the substrate layer, (c) forming or applying one or more polymer interlevel dielectric layers over the substrate layer, at least a first portion of the one or more polymer interlevel dielectric layers being adjacent at least one of the one or more metal layers, (d) forming a trench in the one or more polymer interlevel dielectric layers to separate the first portion from a second portion of the one or more polymer interlevel dielectric layers, and (e) forming or applying a topcoat insulation layer over the one or more polymer interlevel dielectric layers, a portion of the topcoat insulation layer disposed over the trench in at least one of the polymer interlevel dielectric layers to define a moat, the topcoat insulation layer being impervious to moisture, the moat inhibiting moisture from traveling along the one or more polymer interlevel dielectric layers from the second portion to the first portion; and   mounting the semiconductor die on the printed circuit board.   
     
     
         12 . The method of  claim 11  wherein the one or more polymer interlevel dielectric layers are one or more polyimide interlevel dielectric layers. 
     
     
         13 . The method of  claim 11  wherein the one or more polymer interlevel dielectric layers are two polymer interlevel dielectric layers. 
     
     
         14 . The method of  claim 13  wherein the trench is formed in each of the two polymer interlevel dielectric layers in a stepped manner relative to each other. 
     
     
         15 . The method of  claim 11  wherein forming the trench includes etching the one or more polymer interlevel dielectric layers to form the trench. 
     
     
         16 . The method of  claim 11  wherein the one or more metal layers are one or more electrodes of a capacitor. 
     
     
         17 . The method of  claim 11  further comprising forming or applying one or more insulation layers at least partially over at least one of the one or more metal layers. 
     
     
         18 . The method of  claim 11  wherein forming the trench includes tapering the trench toward the substrate layer. 
     
     
         19 . The method of  claim 11  wherein the moat is arranged around a capacitor of the semiconductor die. 
     
     
         20 . The method of  claim 11  wherein the moat is arranged around a plurality of electronic components on the semiconductor die.