Integrated circuit structures including backside vias

Abstract

Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.

1 . An integrated circuit (IC) structure, comprising:
 a device layer, wherein the device layer includes a plurality of active devices;   a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer;   a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and   a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.   
     
     
         2 . The IC structure of  claim 1 , wherein the device layer includes a semiconductor body, and the conductive via is spaced apart from and parallel to the semiconductor body. 
     
     
         3 . The IC structure of  claim 1 , wherein the device layer includes a semiconductor body, and the conductive via is in contact with the semiconductor body. 
     
     
         4 . The IC structure of  claim 1 , wherein the device layer includes a first semiconductor region and a second semiconductor region, the second metallization layer includes a first conductive region under the first semiconductor region, the second metallization layer includes a second conductive region under the second semiconductor region, and an insulating material is between the first conductive region and the second conductive region. 
     
     
         5 . The IC structure of  claim 4 , wherein the first conductive region is a supply voltage region and the second conductive region is a gated supply voltage region. 
     
     
         6 . An integrated circuit (IC) structure, comprising:
 a device layer, wherein the device layer includes an active device region and a dummy region;   a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with the active device region;   a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and   a conductive via in the device layer, wherein the conductive via is in the dummy region, the conductive via is in conductive contact with the first conductive pathway and with the second conductive pathway.   
     
     
         7 . The IC structure of  claim 6 , wherein the dummy region includes a semiconductor body, and the conductive via is spaced apart from and parallel to the semiconductor body. 
     
     
         8 . The IC structure of  claim 7 , further comprising:
 a third conductive pathway, wherein the conductive via is electrically between the second conductive pathway and the third conductive pathway.   
     
     
         9 . The IC structure of  claim 8 , wherein the third conductive pathway is included in the device layer. 
     
     
         10 . An integrated circuit (IC) structure, comprising:
 a device layer, wherein the device layer includes a circuitry region including a transistor region and a diode region;   a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with the circuitry region;   a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and   a conductive via in the device layer, wherein the conductive via is in conductive contact with the circuitry region and also in conductive contact with the second conductive pathway.   
     
     
         11 . The IC structure of  claim 10 , wherein the conductive via is in the diode region. 
     
     
         12 . The IC structure of  claim 11 , further comprising:
 a resistor, wherein the resistor is electrically between the transistor region and the diode region.   
     
     
         13 . The IC structure of  claim 12 , wherein the device layer is between the resistor and the second metallization layer. 
     
     
         14 . The IC structure of  claim 12 , wherein the device layer is between the resistor and the first metallization layer. 
     
     
         15 . The IC structure of  claim 11 , wherein the conductive via is a first conductive via, the IC structure includes a third conductive pathway in the second metallization layer, the IC structure further includes a second conductive via in the device layer, the second conductive via is in conductive contact with the circuitry region and also in conductive contact with the third conductive pathway. 
     
     
         16 . The IC structure of  claim 10 , wherein the device layer includes a dummy region, and the conductive via is in the dummy region. 
     
     
         17 . The IC structure of  claim 16 , wherein the first conductive pathway is electrically between the dummy region and the diode region, and another conductive pathway in the first metallization layer is electrically between the dummy region and the transistor region. 
     
     
         18 . The IC structure of  claim 16 , wherein the conductive via is a first conductive via, the IC structure includes a third conductive pathway in the second metallization layer, the IC structure further includes a second conductive via in the device layer, the second conductive via is in conductive contact with the circuitry region and also in conductive contact with the third conductive pathway. 
     
     
         19 . The IC structure of  claim 18 , wherein the second conductive via is in the transistor region. 
     
     
         20 . The IC structure of  claim 10 , further comprising:
 additional conductive vias in the device layer, wherein some of the additional conductive vias are in the transistor region and electrically couple the transistor region to one or more voltage supply rails, and some of the additional conductive vias are in the diode region and electrically couple the diode region to one or more voltage supply rails.