Methods for fabricating printed circuit board assemblies with high density via array

Abstract

A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.

What is claimed: 
     
         1 . A printed circuit board (PCB) comprising:
 a plurality of layers having a plurality of conductive traces and a plurality of conductive pads; and   a first plurality of plated or filled vias having a first diameter and a second plurality of plated or filled vias having a second diameter on the PCB, wherein the first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias, wherein the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.   
     
     
         2 . The PCB of  claim 1 , wherein the first diameter and the second diameter are different. 
     
     
         3 . The PCB of  claim 1 , wherein the first diameter and the second diameter are the same. 
     
     
         4 . The PCB of  claim 1 , wherein the first plurality of plated or filled vias overlaps with at least a portion of the second plurality of plated or filled vias. 
     
     
         5 . The PCB of  claim 1 , further comprising a third plurality of plated or filled vias having a third diameter among the first plurality of plated or filled vias and the second plurality of plated or filled vias, wherein the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter, the second diameter, and the third diameter. 
     
     
         6 . The PCB of  claim 5 , wherein each of the first plurality of plated or filled vias is surrounded by two or more of the second plurality of plated or filled vias and two or more of the third plurality of plated or filled vias. 
     
     
         7 . The PCB of  claim 1 , wherein each of the first plurality of plated or filled vias is surrounded by two or more of the second plurality of plated or filled vias. 
     
     
         8 . The PCB of  claim 1 , wherein a top surface and a bottom surface of the PCB are coplanar with the remaining surface area. 
     
     
         9 . The PCB of  claim 1 , wherein one or more of the first plurality of plated or filled vias and one or more of the second plurality of plated or filled vias are physically separate while sharing a common electrical ground. 
     
     
         10 . The PCB of  claim 1 , further comprising one or more plated or filled vias at discrete locations. 
     
     
         11 . The PCB of  claim 1 , wherein each of a first filling material in the first plurality of plated or filled vias and a second filling material in the second plurality of plated or filled vias has a thermal conductivity ranging from 0.01 W/mK to 1400 W/mK. 
     
     
         12 . The PCB of  claim 11 , wherein the first filling material or second filling material is one selected from a group consisting of copper, solder, gold, silver, aluminum, conductive paste, plated solid copper, powder metal, micro metal particles, nano metal particles, thermally conductive materials, and combinations thereof. 
     
     
         13 . The PCB of  claim 12 , wherein the first filling material or second filling material comprises a non-conductive material. 
     
     
         14 . The PCB of  claim 12 , wherein the first filling material is different from the second filling material to adjust a coefficient of thermal expansion (CTE) of the PCB. 
     
     
         15 . The PCB of  claim 1 , wherein each of the first plurality of vias and the second plurality of vias comprise through-holes, and/or blind vias. 
     
     
         16 . A printed circuit board (PCB) comprising:
 a plurality of layers having a plurality of conductive traces and a plurality of conductive pads;   a first plurality of plated or filled vias having a first diameter and a second plurality of plated or filled vias having a second diameter on the PCB, wherein the first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias; and   buried conductive traces routed through at least one of the first plurality of plated or filled vias and/or the second plurality of plated or filled vias.   
     
     
         17 . The PCB of  claim 16 , wherein the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter. 
     
     
         18 . The PCB of  claim 16 , wherein the first diameter and the second diameter are different. 
     
     
         19 . The PCB of  claim 16 , wherein the first diameter and the second diameter are the same. 
     
     
         20 . The PCB of  claim 16 , wherein the first plurality of plated or filled vias overlaps with at least a portion of the second plurality of plated or filled vias. 
     
     
         21 . A printed circuit board (PCB) assembly comprising:
 a PCB comprising a plurality of layers having a plurality of conductive traces and a plurality of conductive pads;   surface mount technology (SMT) components mounted on a first side of the PCB; and   a first plurality of plated or filled vias having a first diameter and a second plurality of plated or filled vias having a second diameter on the PCB, wherein the first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias, wherein the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.   
     
     
         22 . The PCB assembly of  claim 21 , wherein one or more of the plurality of conductive traces comprise buried conductive traces routed through at least one of the first plurality of plated or filled vias and/or the second plurality of plated or filled vias, wherein the buried conductive traces are underneath the SMT components and/or around the SMT components. 
     
     
         23 . The PCB assembly of  claim 21 , further comprising a heat sink mounted on a second side of the PCB. 
     
     
         24 . The PCB assembly of  claim 21 , wherein one or more of the plurality of conductive traces comprise exterior or exposed conductive traces and are routed to shorten trace lengths between one or more SMT components. 
     
     
         25 . The PCB of  claim 21 , wherein the first diameter and the second diameter are different. 
     
     
         26 . The PCB of  claim 21 , wherein the first diameter and the second diameter are the same. 
     
     
         27 . The PCB of  claim 21 , wherein the first plurality of plated or filled vias overlaps with at least a portion of the second plurality of plated or filled vias.