Packaging structures

Abstract

Packaging structure includes a substrate; a bonding layer on the substrate; and an improvement layer on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are located in the openings. The chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer. Another packaging structure includes chips and an improvement layer. The chips are interspersed in the improvement layer. Each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer. A gap is formed between each sidewall of the chips and the improvement layer. An encapsulation layer is formed in the gap between each chip and the improvement layer.

What is claimed is: 
     
         1 . A packaging structure, comprising:
 a substrate;   a bonding layer on the substrate;   an improvement layer on the bonding layer, wherein the improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings; and   chips located in the openings, wherein the chips include functional surfaces that bond to the bonding layer, and top surfaces of the chips are lower than or flush with a top surface of the improvement layer.   
     
     
         2 . The structure according to  claim 1 , wherein the bonding layer includes an ultraviolet adhesive, an acrylic pressure sensitive adhesive, or an epoxy pressure sensitive adhesive. 
     
     
         3 . The structure according to  claim 1 , wherein the improvement layer is made of a material including a photoresist. 
     
     
         4 . The structure according to  claim 1 , wherein the substrate is made of a material including glass, ceramic, metal, or polymer. 
     
     
         5 . The structure according to  claim 1 , wherein the chips have a thickness in a range of approximately 20 micrometers to 100 micrometers. 
     
     
         6 . The structure according to  claim 1 , wherein the openings have a depth in a range of approximately 20 micrometers to 100 micrometers. 
     
     
         7 . The structure according to  claim 1 , wherein:
 a difference between a thermal expansion coefficient of the bonding layer and a thermal expansion coefficient of the improvement layer is within a preset range to prevent a relative displacement between the chips and the bonding layer, and   the preset range is between −50 and 50.   
     
     
         8 . A packaging structure, comprising:
 chips;   an improvement layer, wherein:
 the chips are interspersed in the improvement layer, 
 each chip includes a functional surface coplanar with a first surface of the improvement layer, and another surface lower than or flush with a second surface of the improvement layer, and 
 a gap is formed between each sidewall of the chips and the improvement layer; and 
   an encapsulation layer formed in the gap between each chip and the improvement layer.   
     
     
         9 . The structure according to  claim 8 , further including:
 a wiring layer on the functional surface; and   a passivation layer on the wiring layer, wherein the passivation layer includes solder openings that expose surface portions of the wiring layer.   
     
     
         10 . The structure according to  claim 9 , further including:
 solder balls in the solder openings.   
     
     
         11 . The structure according to  claim 10 , wherein the solder balls include gold tin-solder balls, silver-tin solder balls or copper-tin solder balls. 
     
     
         12 . The structure according to  claim 9 , further including:
 the encapsulation layer exposes the another surface of the chip.   
     
     
         13 . The structure according to  claim 9 , wherein a material of the wiring layer includes a metal, including aluminum, copper, tin, nickel, gold, silver, or a combination thereof. 
     
     
         14 . The structure according to  claim 9 , wherein a material of the passivation layer includes polyimide, polyparaphenylene benzobisoxazole or photosensitive benzocyclobutene. 
     
     
         15 . The structure according to  claim 8 , wherein the bonding layer includes an ultraviolet adhesive, an acrylic pressure sensitive adhesive, or an epoxy pressure sensitive adhesive. 
     
     
         16 . The structure according to  claim 8 , wherein the chips have a thickness in a range of approximately 20 micrometers to 100 micrometers. 
     
     
         17 . The structure according to  claim 8 , wherein the improvement layer has a thickness in a range of approximately 20 micrometers to 100 micrometers. 
     
     
         18 . The structure according to  claim 8 , wherein a portion of the encapsulation layer further covers the another surface of the chips and a surface of the improvement layer. 
     
     
         19 . The structure according to  claim 8 , wherein:
 a difference between a thermal expansion coefficient of the bonding layer and a thermal expansion coefficient of the improvement layer is within a preset range to prevent a relative displacement between the chips and the bonding layer, and   the preset range is between −50 and 50.