Radiation-hardened d flip-flop circuit

Abstract

A flip-flop and latch circuit is disclosed. The circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the circuit

What is claimed is: 
     
         1 . A latch circuit comprising:
 a single-input tri-state inverter for receiving an input D;   a dual-input inverter;   a first and second single-event transient (SET) filters;   a dual-input tri-state inverter includes a first input for receiving output signals from the dual-input inverter, a second input for receiving output signals from the dual-input inverter via the first SET filter, and an output for sending output signals to a first input of the dual-input inverter and to a second input of the dual-input inverter via the second SET filter; and   a single-input inverter for receiving inputs from the dual-input inverter to provide an output  Q  for the latch circuit.   
     
     
         2 . The latch circuit of  claim 1 , wherein the dual-input inverter includes a p-channel transistor and an n-channel transistor connected in series between power and ground. 
     
     
         3 . The latch circuit of  claim 1 , wherein the dual-input inverter includes two p-channel transistor and two n-channel transistors connected in series between power and ground. 
     
     
         4 . The latch circuit of  claim 1 , wherein the dual-input tri-state inverter includes a dual-input inverter and a transmission gate. 
     
     
         5 . The latch circuit of  claim 1 , wherein the dual-input tri-state inverter includes two p-channel transistors and two n-channel transistors connected in series between power and ground. 
     
     
         6 . The latch circuit of  claim 1 , wherein the first SET filter includes two inverters connected in series and a capacitor connected between the two inverters. 
     
     
         7 . The latch circuit of  claim 1 , wherein the second SET filter includes two inverters connected in series and a capacitor connected between the two inverters. 
     
     
         8 . A radiation-hardened latch, comprising:
 a single-input tri-state inverter for receiving an input D;   a dual-input inverter;   a first and second single-event transient (SET) filters;   a dual-input tri-state inverter includes a first input for receiving output signals from the dual-input inverter, a second input for receiving output signals from the dual-input inverter via the first SET filter, and an output for sending output signals to a first input of the dual-input inverter and to a second input of the dual-input inverter via the second SET filter; and   a single-input inverter for receiving inputs from the dual-input inverter to provide an output  Q  for the radiation-hardened latch.   
     
     
         9 . The radiation-hardened latch of  claim 8 , further comprising a clock signal (CLK) tied to the single tri-state inverter, wherein the input D enters the single-input tri-state inverter when the clock signal CLK goes to a logical low. 
     
     
         10 . The radiation-hardened latch of  claim 8 , wherein the output signals from the dual-input inverter only changes state when signals at both the first input and the second input of the dual-input inverter are the same. 
     
     
         11 . The radiation-hardened latch of  claim 8 , wherein the output signals from the dual-input inverter goes simultaneously to the single-input inverter and to another temporal filter formed by the dual-input tri-state inverter and the first SET filter. 
     
     
         12 . The radiation-hardened latch of  claim 8 , wherein the dual input inverter and the second SET filter form a temporal filter. 
     
     
         13 . The radiation-hardened latch of  claim 8 , wherein the dual input inverter and the second SET filter form a first temporal filter, and the dual-input tri-state inverter and the first SET filter form a second temporal filter. 
     
     
         14 . The radiation-hardened latch of  claim 13 , wherein the first temporal filter and second temporal filter hold the input data D when the clock signal CLK goes to a logical high. 
     
     
         15 . The radiation-hardened latch of  claim 8 , wherein the dual-input inverter includes a p-channel transistor and an n-channel transistor connected in series between power and ground. 
     
     
         16 . The radiation-hardened latch of  claim 8 , wherein the dual-input inverter includes two p-channel transistor and two n-channel transistors connected in series between power and ground. 
     
     
         17 . The radiation-hardened latch of  claim 8 , wherein the dual-input tri-state inverter includes a dual-input inverter and a transmission gate. 
     
     
         18 . The radiation-hardened latch of  claim 8 , wherein the dual-input tri-state inverter includes two p-channel transistors and two n-channel transistors connected in series between power and ground. 
     
     
         19 . The radiation-hardened latch of  claim 8 , wherein the first SET filter includes two inverters connected in series and a capacitor connected between the two inverters. 
     
     
         20 . The radiation-hardened latch of  claim 8 , wherein the second SET filter includes two inverters connected in series and a capacitor connected between the two inverters.