At-speed test of functional memory interface logic in devices

Abstract

A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

What is claimed is: 
     
         1 . A method of testing a functional memory interface logic at-speed, the method comprising:
 generating test sequences for memory of a core under test by a built-in-self-test (BIST) controller;   selectively enable clocks to drive the test sequences to an input of the memory or to capture the output of the memory;   selecting a slow-speed or at-speed operation for an enabled clock;   selecting a test mode on the input of the memory or the output of the memory, wherein the selective control of the test mode is implemented during the selected slow-speed or at-speed operation of the enabled clock.   
     
     
         2 . The method of  claim 1 , wherein the memory includes multiple memories coupled to another and tested independent of one another. 
     
     
         3 . The method of  claim 1 , wherein the test mode includes a BIST mode or a functional mode. 
     
     
         4 . The method of  claim 1 , wherein the selecting the test mode includes switching to a BIST mode to initialize the memory at slow-speed of the enabled clock, wherein initialization is implemented using a BIST controller logic for one or more slow-speed scan capture cycles. 
     
     
         5 . The method of  claim 4 , wherein the test mode is switched back to a functional mode to execute a memory output interface logic, wherein the functional mode uses the at-speed operation of the enabled clock. 
     
     
         6 . The method of  claim 5 , wherein the enabled clock to the memory output interface BIST logic is disabled when exercising memory output in functional mode for two or more at-speed scan capture cycles. 
     
     
         7 . The method of  claim 4 , wherein the test mode is switched back to the BIST mode after two or more at-speed scan capture cycles, wherein the BIST mode includes the slow-speed operation of the enabled clock to obtain logic results for the two or more at-speed capture cycles. 
     
     
         8 . The method of  claim 1 , wherein the test mode is selected to be a functional mode and at-speed operation of the enabled clock to execute a test on the memory input interface logic, wherein the test mode is switched back to a BIST mode after two or more at-speed scan capture cycles, wherein the BIST mode includes the slow-speed operation of the enabled clock to obtain logic results for the two or more at-speed capture cycles. 
     
     
         9 . A method comprising:
 generating test sequences for memory of a core under test by a built-in-self-test (BIST) controller;   selectively enabling clocks to drive the test sequences to a memory input or to capture the output of the memory of the core under tests;   selectively providing a slow-speed or at-speed operation for an enabled clock;   selectively controlling a BIST mode or a functional mode on the input of the memory or output of the memory, wherein the BIST mode is implemented using the slow-speed operation while the functional mode utilizes the at-speed operation for the enabled clock.   
     
     
         10 . The method of  claim 9 , wherein the memory is initialized at slow-speed using the BIST mode, wherein the initialization is implemented using a BIST controller logic for one or more slow-speed scan capture cycles. 
     
     
         11 . The method of  claim 10 , wherein an at-speed functional mode is used to execute a memory output interface logic or a memory input interface logic, wherein a slow-speed BIST mode is used to obtain logic results after two or more at-speed capture cycles.