Stacked field-effect transistors having proximity electrodes and proximity bias circuits

Abstract

Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.

What is claimed is: 
     
         1 . A stack of field-effect transistor (FET) devices comprising:
 a first node;   a second node;   a proximity bias circuit configured to provide the proximity bias signal; and   a plurality of FET devices arranged in series between the first node and the second node, each FET device including an insulator layer, a substrate layer under the insulator layer, and a FET implemented on an active silicon layer formed over the insulator layer, with a subset of the FET devices including a proximity electrode implemented adjacent to a corresponding FET and configured to receive the proximity bias signal and to generate an electric field between the proximity electrode and a region generally underneath the corresponding FET.   
     
     
         2 . The stack of FET devices of  claim 1  wherein each FET device of the subset of FET devices includes a substrate contact feature implemented to provide an electrical connection to the substrate layer. 
     
     
         3 . The stack of FET devices of  claim 2  further comprising a substrate bias circuit configured to provide a substrate bias signal to the substrate contact features. 
     
     
         4 . The stack of FET devices of  claim 2  wherein, for each FET device of the subset of FET devices, the substrate contact feature is positioned to be laterally spaced from the FET by a distance greater than a lateral spacing of the proximity electrode from the FET. 
     
     
         5 . The stack of FET devices of  claim 1  wherein the proximity electrode is positioned to be laterally offset from a nearest edge of the corresponding FET by a distance that is less than 10 μm. 
     
     
         6 . A stack of field-effect transistor (FET) devices comprising:
 a first node;   a second node;   a plurality of FET devices arranged in series between the first node and the second node, each FET device including an insulator layer, a substrate layer under the insulator layer, and a FET implemented on an active silicon layer formed over the insulator layer, with a subset of the FET devices including a proximity electrode implemented adjacent to a corresponding FET and configured to receive a proximity bias signal and to generate an electric field between the proximity electrode and a region generally underneath the corresponding FET;   a first proximity bias circuit configured to provide a first proximity bias signal to a first portion of the subset of FET devices; and   a second proximity bias circuit configured to provide a second proximity bias signal to a second portion of the subset of FET devices.   
     
     
         7 . The stack of FET devices of  claim 6  wherein each FET device of the subset of FET devices includes a substrate contact feature implemented to provide an electrical connection to the substrate layer. 
     
     
         8 . The stack of FET devices of  claim 7  further comprising a substrate bias circuit configured to provide a substrate bias signal to the substrate contact features. 
     
     
         9 . The stack of FET devices of  claim 7  wherein, for each FET device of the subset of FET devices, the substrate contact feature is positioned to be laterally spaced from the FET by a distance greater than a lateral spacing of the proximity electrode from the FET. 
     
     
         10 . The stack of FET devices of  claim 6  wherein each FET device of the subset of FET devices receives a separate proximity bias signal. 
     
     
         11 . The stack of FET devices of  claim 6  wherein the proximity electrode is positioned to be laterally offset from a nearest edge of the corresponding FET by a distance that is less than 10 μm. 
     
     
         12 . A stack of field-effect transistor (FET) devices comprising:
 a first node;   a second node; and   a plurality of FET devices arranged in series between the first node and the second node, each FET device including an insulator layer, a substrate layer under the insulator layer, and a FET implemented on an active silicon layer formed over the insulator layer, with each FET of the plurality of FET devices including a proximity electrode implemented adjacent to a corresponding FET and configured to receive a proximity bias signal and to generate an electric field between the proximity electrode and a region generally underneath the corresponding FET.   
     
     
         13 . The stack of FET devices of  claim 12  further comprising a proximity bias circuit configured to provide the proximity bias signal. 
     
     
         14 . The stack of FET devices of  claim 13  wherein each FET device of the plurality of FET devices includes a substrate contact feature implemented to provide an electrical connection to the substrate layer. 
     
     
         15 . The stack of FET devices of  claim 14  further comprising a substrate bias circuit configured to provide a substrate bias signal to the substrate contact features. 
     
     
         16 . The stack of FET devices of  claim 14  wherein, for each FET device of the plurality of FET devices, the substrate contact feature is positioned to be laterally spaced from the FET by a distance greater than a lateral spacing of the proximity electrode from the FET. 
     
     
         17 . The stack of FET devices of  claim 12  further comprising a first proximity bias circuit configured to provide a first proximity bias signal to a first portion of the plurality of FET devices and a second proximity bias circuit configured to provide a second proximity bias signal to a second portion of the plurality of FET devices. 
     
     
         18 . The stack of FET devices of  claim 12  wherein the plurality of FET devices receives a common proximity bias signal. 
     
     
         19 . The stack of FET devices of  claim 12  wherein each FET device of the plurality of FET devices receives a separate proximity bias signal. 
     
     
         20 . The stack of FET devices of  claim 12  wherein the proximity electrode is positioned to be laterally offset from a nearest edge of the corresponding FET by a distance that is less than 10 μm.