Systems and methods for executing a fused multiply-add instruction for complex numbers

Abstract

Disclosed embodiments relate to executing a vector-complex fused multiply-add Instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.

1 .- 20 . (canceled) 
     
     
         21 . A processor comprising:
 a fetch circuit to fetch a single instruction specifying an opcode and locations of a first source and a second source comprising complex numbers, and a destination vector, the opcode indicating an execution circuit is to, for each corresponding pair of complex numbers of the first and second sources, generate in parallel with a respective multiplier circuit, a product of their real components, a product of their imaginary components, and two mixed products, and use the four products to generate a complex result for each corresponding element of the destination vector;   a decode circuit to decode the single instruction; and   the execution circuit to execute the single instruction as per the opcode, and store each of the complex results in the corresponding element of the destination vector.   
     
     
         22 . The processor of  claim 21 , wherein the opcode comprises a first value that indicates a vector-complex fused multiply add (VCFMADD), and the execution circuit, when using the four products, is to:
 generate a real component of multiple complex results by subtracting the product of imaginary components from the product of real components; and   generate an imaginary component of multiple complex results by adding the two mixed products.   
     
     
         23 . The processor of  claim 22 , wherein the opcode comprises a second value, different than the first value, that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the execution circuit, when using the four products, is to:
 generate a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generate an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         24 . The processor of  claim 21 , wherein the opcode comprises a value that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the execution circuit, when using the four products, is to:
 generate a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generate an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         25 . The processor of  claim 21 , wherein the single instruction further includes a field to identify a write mask comprising multiple bits, each bit to specify whether a corresponding element of the destination vector is to be masked, in which case the execution circuit is either to set the element to zero or leave the element unchanged. 
     
     
         26 . The processor of  claim 21 , wherein the opcode indicates the execution circuit is to, for each corresponding pair of complex numbers of a plurality of complex numbers in each of the first and second sources, generate in parallel with the respective multiplier circuit, the product of their real components, the product of their imaginary components, and two mixed products, and use the four products to generate the complex result for each corresponding element of the destination vector. 
     
     
         27 . The processor of  claim 21 , wherein the opcode indicates the execution circuit is further to, for a single complex number in the first source, broadcast the single complex number to a same vector length of the destination vector for use by the execution circuit in executing the single instruction. 
     
     
         28 . The processor of  claim 21 , wherein a width of each element of the first source, the second source, and the destination vector is indicated by a prefix to the opcode. 
     
     
         29 . A method comprising:
 fetching, by a fetch circuit of a processor, a single instruction specifying an opcode and locations of a first source and a second source comprising complex numbers, and a destination vector, the opcode indicating an execution circuit is to, for each corresponding pair of complex numbers of the first and second sources, generate in parallel with a respective multiplier circuit, a product of their real components, a product of their imaginary components, and two mixed products, and use the four products to generate a complex result for each corresponding element of the destination vector;   decoding, by a decode circuit of the processor, the single instruction; and   executing, by the execution circuit of the processor, the single instruction as per the opcode, and storing each of the complex results in the corresponding element of the destination vector.   
     
     
         30 . The method of  claim 29 , wherein the opcode comprises a first value that indicates a vector-complex fused multiply add (VCFMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by subtracting the product of imaginary components from the product of real components; and   generating an imaginary component of multiple complex results by adding the two mixed products.   
     
     
         31 . The method of  claim 30 , wherein the opcode comprises a second value, different than the first value, that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generating an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         32 . The method of  claim 29 , wherein the opcode comprises a value that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generating an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         33 . The method of  claim 29 , wherein the single instruction further includes a field identifying a write mask comprising multiple bits, each bit specifying whether a corresponding element of the destination vector is to be masked, in which case the execution circuit is either to set the element to zero or leave the element unchanged. 
     
     
         34 . The method of  claim 29 , wherein the opcode indicates the execution circuit is to, for each corresponding pair of complex numbers of a plurality of complex numbers in each of the first and second sources, generate in parallel with the respective multiplier circuit, the product of their real components, the product of their imaginary components, and two mixed products, and use the four products to generate the complex result for each corresponding element of the destination vector. 
     
     
         35 . The method of  claim 29 , wherein the opcode indicates the execution circuit is further to, for a single complex number in the first source, broadcast the single complex number to a same vector length of the destination vector for use by the execution circuit in executing the single instruction. 
     
     
         36 . The method of  claim 29 , wherein a width of each element of the first source, the second source, and the destination vector is indicated by a prefix to the opcode. 
     
     
         37 . A method comprising:
 fetching, by a fetch circuit of the processor, a single instruction, of a first instruction set architecture, specifying an opcode and locations of a first source and a second source comprising complex numbers, and a destination vector, the opcode indicating an execution circuit is to, for each corresponding pair of complex numbers of the first and second sources, generate in parallel with a respective multiplier circuit, a product of their real components, a product of their imaginary components, and two mixed products, and use the four products to generate a complex result for each corresponding element of the destination vector;   translating the single instruction of the first instruction set architecture into one or more instructions of a second instruction set architecture;   decoding, by a decode circuit of the processor, the one or more instructions of the second instruction set architecture; and   executing, by the execution circuit of the processor, the one or more instructions of the second instruction set architecture as per the opcode, and storing each of the complex results in the corresponding element of the destination vector.   
     
     
         38 . The method of  claim 37 , wherein the opcode comprises a first value that indicates a vector-complex fused multiply add (VCFMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by subtracting the product of imaginary components from the product of real components; and   generating an imaginary component of multiple complex results by adding the two mixed products.   
     
     
         39 . The method of  claim 38 , wherein the opcode comprises a second value, different than the first value, that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generating an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         40 . The method of  claim 37 , wherein the opcode comprises a value that indicates a vector-complex fused conjugated multiply add (VCFCMADD), and the executing, using the four products, comprises:
 generating a real component of multiple complex results by adding the product of imaginary components and the product of real components; and   generating an imaginary component of multiple complex results by subtracting one of the two mixed products from the other of the two mixed products.   
     
     
         41 . The method of  claim 37 , wherein the single instruction further includes a field identifying a write mask comprising multiple bits, each bit specifying whether a corresponding element of the destination vector is to be masked, in which case the execution circuit is either to set the element to zero or leave the element unchanged. 
     
     
         42 . The method of  claim 37 , wherein the opcode indicates the execution circuit is to, for each corresponding pair of complex numbers of a plurality of complex numbers in each of the first and second sources, generate in parallel with the respective multiplier circuit, the product of their real components, the product of their imaginary components, and two mixed products, and use the four products to generate the complex result for each corresponding element of the destination vector. 
     
     
         43 . The method of  claim 37 , wherein the opcode indicates the execution circuit is further to, for a single complex number in the first source, broadcast the single complex number to a same vector length of the destination vector for use by the execution circuit in executing the single instruction. 
     
     
         44 . The method of  claim 37 , wherein a width of each element of the first source, the second source, and the destination vector is indicated by a prefix to the opcode.