US2021399195A1PendingUtilityA1

Quantum device

Assignee: NEC CORPPriority: Jun 19, 2020Filed: Jun 9, 2021Published: Dec 23, 2021
Est. expiryJun 19, 2040(~13.9 yrs left)· nominal 20-yr term from priority
H10W 40/10H10W 70/68H10W 40/228H10W 72/20H10W 72/07251H10W 90/401H10W 70/668G06N 10/40H01L 39/045H10N 69/00H10N 60/815
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Claims

Abstract

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device 1 includes a quantum chip 10 and an interposer 20 on which the quantum chip 10 is located. The interposer 20 includes an interposer substrate 22 and an interposer wiring layer 30. The interposer wiring layer 30 is disposed on a surface 22a of the interposer substrate 22 on a side on which the quantum chip 10 is located. The interposer wiring layer 30 includes, in at least a part thereof, a superconducting material layer 32 formed of a superconducting material and a non-superconducting material layer 34 formed of a non-superconducting material.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A quantum device comprising:
 a quantum chip; and   an interposer on which the quantum chip is mounted, wherein   the interposer comprises:   a substrate; and   a wiring layer disposed on a surface of the substrate on a side thereof on which the quantum chip is located, and   the wiring layer comprises, in at least a part thereof, a first metal layer formed of a superconducting material and a second metal layer formed of a non-superconducting material.   
     
     
         2 . The quantum device according to  claim 1 , wherein the wiring layer comprises, in a first area thereof, the first metal layer and the second metal layer, the first area being at least a predetermined part of the wiring layer. 
     
     
         3 . The quantum device according to  claim 2 , wherein the first metal layer is a metal layer closest to the quantum chip at least in the first area. 
     
     
         4 . The quantum device according to  claim 2 , wherein a thickness of the second metal layer in the wiring layer is larger than that of the first metal layer in the wiring layer. 
     
     
         5 . The quantum device according to  claim 2 , wherein the first area corresponds to an area of the wiring layer that is opposed to the quantum chip. 
     
     
         6 . The quantum device according to  claim 5 , wherein a surface of the wiring layer on a side thereof on which the quantum chip is located is formed of a non-superconducting material at least in a part of the wiring layer located outside the first area thereof. 
     
     
         7 . The quantum device according to  claim 6 , wherein the interposer is configured so that when the quantum device is cooled, a surface of the wiring layer formed of the non-superconducting material, located in an area outside the first area of the wiring layer comes into contact with a sample stage having a cooling function. 
     
     
         8 . The quantum device according to  claim 1 , wherein the interposer is configured so that when the quantum device is cooled, at least the second metal layer comes into contact with a sample stage having a cooling function. 
     
     
         9 . The quantum device according to  claim 1 , wherein
 a via is formed in the substrate, the via being formed of a non-superconducting material and penetrating the substrate, and   the interposer is configured so that when the quantum device is cooled, at least a surface of the interposer on a side opposite to a side thereof on which the quantum chip is located is cooled.

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