Configurable Three-Dimensional Neural Network Array

Abstract

Configurable three-dimensional neural network array. In an exemplary embodiment, a three-dimensional (3D) neural network array includes a plurality of stacked synapse layers having a first orientation, and a plurality of synapse lines having a second orientation and passing through the synapse layers. The neural network array also includes synapse elements connected between the synapse layers and synapse lines. Each synapse element includes a programmable resistive element. The neural network array also includes a plurality of output neurons, and a plurality of select transistors connected between the synapse lines and the output neurons. The gate terminals of the select transistors receive input signals.

What is claimed is: 
     
         1 . A three-dimensional (3D) neural network array, comprising:
 a plurality of stacked synapse layers having a first orientation;   a plurality of synapse lines having a second orientation and passing through the synapse layers;   synapse elements connected between the synapse layers and synapse lines, and wherein each synapse element includes a programmable resistive element;   a plurality of output neurons; and   a plurality of select transistors connected between the synapse lines and the output neurons, and wherein gates of the select transistors receive input signals.   
     
     
         2 . The 3D neural network of  claim 1 , wherein the select transistors are configured as one of PMOS or NMOS transistors. 
     
     
         3 . The 3D neural network of  claim 1 , wherein the select transistors are configured as native transistors having little or substantially no voltage drop. 
     
     
         4 . The 3D neural network of  claim 1 , wherein the first orientation is horizontal and the second orientation is vertical. 
     
     
         5 . The 3D neural network of  claim 1 , wherein each programmable resistive element comprises material selected from a set of materials comprising resistive material, phase change material, ferroelectric material, and magnetic material. 
     
     
         6 . The 3D neural network of  claim 1 , wherein each synapse element includes a diode. 
     
     
         7 . The 3D neural network of  claim 6 , wherein the diodes comprise at least one of diode material, Schottky diode material, NbOx material, TaOx material and VCrOx material. 
     
     
         8 . The 3D neural network of  claim 1 , further comprising pull-up transistors coupled to the output neurons. 
     
     
         9 . The 3D neural network of  claim 1 , further comprising pull-down transistors coupled to the output neurons. 
     
     
         10 . The 3D neural network of  claim 1 , wherein the output neurons are formed as surface diffusions. 
     
     
         11 . The 3D neural network of  claim 1 , further comprising conductive contacts connected to the output neurons. 
     
     
         12 . The 3D neural network of  claim 10 , wherein the conductive contacts further comprise in-line pass transistors. 
     
     
         13 . The 3D neural network of  claim 12 , wherein the pass transistors are formed as planar transistors. 
     
     
         14 . The 3D neural network of  claim 13 , wherein the 3D neural network forms a first neural network layer and wherein the conductive contacts are connected between the output neurons and gate terminals of select transistors associated with a second neural network layer. 
     
     
         15 . The 3D neural network of  claim 14 , wherein the pass transistors are enabled or disabled to control signals flowing from the first neural network layer to the second neural network layer. 
     
     
         16 . The 3D neural network of  claim 1 , wherein the 3D neural network array is stacked on a semiconductor device so that the 3D neural network array uses no additional semiconductor surface area. 
     
     
         17 . A method for generating a 3D neural network array, the method comprising operations of:
 forming output neuron layers;   forming select gates on the output neuron layers, wherein the select gates cross from a first output neuron layer to an adjacent output neuron layer;   forming vertical channels on the select gates, wherein landing pads are formed on top of the vertical channels;   forming multiple synapse layers on top of the select gates; and   forming synapse lines through the synapse layers, wherein the synapse lines connect to corresponding landing pads.