Embedded semiconductive chips in reconstituted wafers, and systems containing same

Abstract

A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

What is claimed is: 
     
         1 . A microelectronic package, comprising:
 a first semiconductor die having first terminals extending from an active side of the first semiconductor die;   a second semiconductor die having second terminals extending from an active side of the second semiconductor die;   an encapsulation mass wherein a backside surface of the encapsulation mass is coplanar with a backside surface of the first semiconductor die and a backside surface of the second semiconductor die; and   at least one dielectric layer and at least one metallization over the first terminals and second terminals, wherein the at least one metallization electrically connects the first semiconductor die and the second semiconductor die.   
     
     
         2 . The microelectronic package of  claim 1 , wherein a topside of the encapsulation mass is coplanar with the first terminals and the second terminals. 
     
     
         3 . The microelectronic package of  claim 2 , wherein a topside of the encapsulation mass and the first terminals and the second terminals include a mechanically planarized surface. 
     
     
         4 . The microelectronic package of  claim 1 , wherein the first semiconductor die includes a processor and wherein the second semiconductor die includes a memory die. 
     
     
         5 . The microelectronic package of  claim 1 , wherein the encapsulation mass includes epoxy. 
     
     
         6 . A microelectronic package, comprising:
 a first semiconductor die having first terminals extending from an active side of the first semiconductor die;   a second semiconductor die having second terminals extending from an active side of the second semiconductor die;   an encapsulation mass wherein a backside surface of the encapsulation mass is coplanar with a backside surface of the first semiconductor die and a backside surface of the second semiconductor die;   a plurality of layers, including at least one dielectric layer and at least one metallization over the first terminals and second terminals, wherein the at least one metallization electrically connects the first semiconductor die and the second semiconductor die; and   an RF die coupled to the plurality of layers on a side opposite the first semiconductor die and the second semiconductor die.   
     
     
         7 . The microelectronic package of  claim 6 , wherein the RF die is wirebonded to the plurality of layers. 
     
     
         8 . The microelectronic package of  claim 6 , further including a passive device coupled to the plurality of layers on the side opposite the first semiconductor die and the second semiconductor die. 
     
     
         9 . The microelectronic package of  claim 8 , wherein the passive device includes an inductor. 
     
     
         10 . The microelectronic package of  claim 8 , wherein the passive device includes a capacitor. 
     
     
         11 . The microelectronic package of  claim 8 , wherein the passive device is attached to the plurality of layers using solder. 
     
     
         12 . The microelectronic package of  claim 8 , further including a third semiconductor die on adjacent to the first semiconductor die and the second semiconductor die wherein a backside surface of the third semiconductor die is coplanar with the backside surface of the encapsulation mass. 
     
     
         13 . The microelectronic package of  claim 12 , further including a fourth semiconductor die on adjacent to the first semiconductor die and the second semiconductor die wherein a backside surface of the fourth semiconductor die is coplanar with the backside surface of the encapsulation mass. 
     
     
         14 . The microelectronic package of  claim 13 , further including a fifth semiconductor die on adjacent to the first semiconductor die and the second semiconductor die wherein a backside surface of the fifth semiconductor die is coplanar with the backside surface of the encapsulation mass. 
     
     
         15 . The microelectronic package of  claim 6 , wherein a topside of the encapsulation mass is coplanar with the first terminals and the second terminals. 
     
     
         16 . The microelectronic package of  claim 15 , wherein a topside of the encapsulation mass and the first terminals and the second terminals include a mechanically planarized surface. 
     
     
         17 . The microelectronic package of  claim 6 , wherein the first semiconductor die includes a processor and wherein the second semiconductor die includes a memory die. 
     
     
         18 . The microelectronic package of  claim 6 , wherein the encapsulation mass includes epoxy.