Multilayers of nickel alloys as diffusion barrier layers

Abstract

A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a 1 . The structure also includes a second Ni alloy layer with a Ni grain size a 2 , wherein a 1 <a 2 . The first Ni alloy layer is between the Cu layer and the second Ni alloy layer. The structure further includes a tin (Sn) layer. The second Ni alloy layer is between the first Ni alloy layer and the Sn layer.

What is claimed is: 
     
         1 . A method of forming an integrated circuit package, the method comprising:
 forming a die; and   forming a bump on the die such that the bump is electrically connected to the die, the forming of the bump comprises:   forming a first nickel (Ni) alloy layer, with a Ni grain size a 1 , over a copper (Cu) layer;   forming a second Ni alloy layer, with a Ni grain size a 2 , over the first Ni alloy layer, wherein a 1 <a 2 ; and   forming a tin (Sn) layer over the second Ni alloy layer, wherein the alloy in in the first Ni alloy layer and the second Ni alloy layer is co-deposited with Ni, and a percentage weight of the alloy in the first Ni alloy layer and the second Ni alloy layer is controlled at an atomic order.   
     
     
         2 . The method of  claim 1 , wherein the first Ni alloy layer and the second Ni alloy layer each comprises at least one element selected from the group consisting of tungsten (W), molybdenum (Mo), an element from a lanthanoid group, and combinations thereof. 
     
     
         3 . The method of  claim 2 , wherein a % by weight (x 1 ) of the at least one element within the first Ni alloy layer is present, a % by weight (x 2 ) of the at least one element within the second Ni alloy layer is present, and wherein x 1 >x 2 . 
     
     
         4 . The method of  claim 1 , wherein the copper layer is over a pad of the die. 
     
     
         5 . The method of  claim 1 , wherein the first nickel alloy layer and the second nickel alloy layer include one of NiCe, NiMoW, and NiWCe. 
     
     
         6 . A method of forming an integrated circuit package, the method comprising:
 forming a die; and   forming a bump on the die such that the bump is electrically connected to the die, the forming of the bump comprises:   forming a copper (Cu) layer;   forming a nickel (Ni) alloy layer with Ni grain sizes a 1  and a 2 , wherein a 1 <a 2 ; and   forming a tin (Sn) layer, wherein the Ni alloy layer is between the Cu layer and the Sn layer; wherein the alloy in in the Ni alloy layer and the is co-deposited with Ni, and a percentage weight of the alloy in the Ni alloy layer is controlled at an atomic order.   
     
     
         7 . The method of  claim 6 , wherein the Ni grains of size a 1  within the Ni alloy layer is substantially closer to the Cu layer than the Sn layer, and the Ni grains of size a 2  within the Ni alloy layer is substantially closer to the Sn layer than the Cu layer. 
     
     
         8 . The method of  claim 6 , wherein the Ni alloy layer comprises at least one element selected from the group consisting of tungsten (W), molybdenum (Mo), an element from a lanthanoid group, and combinations thereof. 
     
     
         9 . The method of  claim 8 , wherein a % by weight (x 1 ) of the at least one element within the Ni alloy layer is present, a % by weight (x 2 ) of the at least one element within the Ni alloy layer is present, and wherein x 1 >x 2 . 
     
     
         10 . The method of  claim 9 , wherein the at least one element at x 1  within the Ni alloy layer is substantially closer to the Sn layer than the Cu layer, and the at least one element at x 2  within the Ni alloy layer is substantially closer to the Cu layer than the Sn layer. 
     
     
         11 . A method of forming an integrated circuit package, the method comprising:
 forming a die; and   forming a bump on the die such that the bump is electrically connected to the die, the forming of the bump comprises:   forming a first nickel (Ni) alloy layer via a reversed pulse electrodeposition process, with a Ni grain size a 1 , over a copper (Cu) layer;   forming a second Ni alloy layer via the reversed pulse electrodeposition process, with a Ni grain size a 2 , over the first Ni alloy layer, wherein a 1 <a 2 ; and   forming a tin (Sn) layer over the second Ni alloy layer.   
     
     
         12 . The method of  claim 11 , wherein the first Ni alloy layer and the second Ni alloy layer each comprises at least one element selected from the group consisting of tungsten (W), molybdenum (Mo), an element from a lanthanoid group, and combinations thereof. 
     
     
         13 . The method of  claim 12 , wherein a % by weight (x 1 ) of the at least one element within the first Ni alloy layer is present, a % by weight (x 2 ) of the at least one element within the second Ni alloy layer is present, and wherein x 1 >x 2 . 
     
     
         14 . The method of  claim 11 , wherein the copper layer is over a pad of the die. 
     
     
         15 . The method of  claim 11 , wherein the first nickel alloy layer and the second nickel alloy layer include one of NiCe, NiMoW, and NiWCe.