Circuit board and method for manufacturing the same

Abstract

The present application provides a circuit board and a manufacturing method therefor. The circuit board includes: a core board, at least one chip, a first circuit layer, and a first insulating layer. A groove body is formed on the core board. The chip is provided in the groove body. The chip is provided with a first lead-out terminal. The first circuit layer is provided on at least one side of the core board. The first insulating layer is provided between the core board and the first circuit layer. The first lead-out terminal passes through the first insulating layer and is connected to the first circuit layer, so that the chip is electrically connected to the first circuit layer. Thus, the wiring between the chip and the circuit is more flexible.

What is claimed is: 
     
         1 . A circuit board, comprising:
 a core board, defining a groove;   at least one chip, received in the groove, wherein the chip has a first lead terminal;   a first circuit layer, arranged on at least one side of the core board;   a first insulating layer, disposed between the core board and the first circuit layer;   wherein the first lead terminal extends through the first insulating layer to be connected to the first circuit layer, enabling the chip to be electrically connected to the first circuit layer.   
     
     
         2 . The circuit board according to  claim 1 , further comprising:
 a second circuit layer, arranged on a side of the first circuit layer away from the core board;   a second insulating layer, disposed between the first circuit layer and the second circuit layer;   wherein the second insulating layer is configured with a second lead terminal to electrically connect the second circuit layer to the first circuit layer, enabling the chip to be electrically connected to the second circuit layer.   
     
     
         3 . The circuit board according to  claim 2 , further comprising:
 a third circuit layer, arranged on a side of the second circuit layer away from the core board;   a third insulating layer, disposed between the second circuit layer and the third circuit layer;   wherein the third insulating layer is configured with a third lead terminal to electrically connect the third circuit layer to the second circuit layer, enabling the chip to be electrically connected to the third circuit layer.   
     
     
         4 . The circuit board according to  claim 1 , wherein,
 the first circuit layer is arranged with a plurality of first circuit networks, the plurality of first circuit networks are different from each other; and   the chip is electrically connected to the plurality of first line networks via different first lead terminals.   
     
     
         5 . The circuit board according to  claim 3 , wherein,
 the second circuit layer is arranged with a plurality of second circuit networks, the plurality of second circuit networks are different from each other;   the second lead terminal electrically connects the first circuit networks, which are connected to the first lead terminals, to the second circuit network, enabling the chip to be electrically connected to the second circuit networks;   the third circuit layer is arranged with a plurality of third circuit networks, the plurality of third circuit networks are different from each other;   the third lead terminal electrically connects the second circuit networks, which are connected to the second lead terminal, to the third circuit networks, enabling the chip to be electrically connected to the third circuit networks.   
     
     
         6 . The circuit board according to  claim 2 , wherein
 the first circuit layer is arranged with a plurality of first circuit networks; and   the second circuit layer is arranged with a plurality of second circuit networks.   
     
     
         7 . The circuit board according to  claim 6 , wherein the number of first circuit networks is equal to the number of second circuit networks. 
     
     
         8 . The circuit board according to  claim 7 , wherein the number of first lead terminal is equal to the number of second lead terminal. 
     
     
         9 . The circuit board according to  claim 6 , wherein the number of second circuit networks is n times of the number of first circuit networks. 
     
     
         10 . The circuit board according to  claim 6 , wherein the number of second lead terminals is n times the number of first lead terminals. 
     
     
         11 . The circuit board according to  claim 5 , wherein,
 the number of second lead terminals is n times of the number of first lead terminals, the n is an integer;   the number of third lead terminals is m times of the number of second lead terminals, the m is an integer.   
     
     
         12 . The circuit board according to  claim 6 , wherein each of the first lead terminal, the second lead terminal and the third lead terminal is any one or a combination of a copper post or a conductive through hole. 
     
     
         13 . The circuit board according to  claim 6 , wherein a pad is arranged at each of two connective ends of the first lead terminal, each of two connective ends of the second lead terminal, and each of two connective ends of the third lead terminal. 
     
     
         14 . The circuit board according to  claim 5 , wherein any one of the second circuit networks is connected to any one of the third circuit networks, and each connection is achieved via one third lead terminal. 
     
     
         15 . The circuit board according to  claim 1 , wherein,
 the groove is a through groove running through two surfaces of the core board; or   the groove is a blind groove running through one surface of the core board;   wherein a distance between the chip and a side wall of the groove is 20 μm to 50 μm, and molding silicone is disposed between the chip and the side wall of the groove.   
     
     
         16 . The circuit board according to  claim 3 , wherein,
 a thickness of each of the first insulating layer, the second insulating layer, the third insulating layer, the first circuit layer, the second circuit layer and the third circuit layer is 10 μm to 40 μm.   
     
     
         17 . The circuit board according to  claim 3 , wherein,
 a thickness of each of the first insulating layer, the second insulating layer and the third insulating layer is 30 μm; and   a thickness of each of the first circuit layer, the second circuit layer and the third circuit layer is 18 μm.   
     
     
         18 . The circuit board according to  claim 3 , wherein each of the first insulating layer, the second insulating layer and the third insulating layer are curable adhesive substance; and the core board is a copper-clad board. 
     
     
         19 . A method of manufacturing the circuit board, comprising:
 providing a core board;   defining a groove in the core board;   placing a chip in the groove and exposing a first lead terminal;   defining a first through hole in a first insulating layer at a position corresponding to the first lead terminal; and   arranging the first insulating layer and the first circuit layer successively on at least one side of the core board, allowing the first lead terminal to extend through the first through hole to be electrically connected to the first circuit layer.   
     
     
         20 . The method according to  claim 19 , further comprising:
 defining a second through hole in a second insulating layer at a predetermined position, and arranging a conductive layer in the second through hole;   arranging a second insulating layer and a second circuit layer successively on an outside of the first circuit layer, allowing the first circuit layer to be electrically connected to the second circuit layer through the second through hole;   defining a third through hole at a predetermined position in the third insulating layer, and arranging a conductive layer in the third through hole; and   arranging a third insulating layer and a third circuit layer successively on an outside of the second circuit layer, allowing the third circuit layer to be electrically connected to the second circuit layer through the third through hole.