Selective removal of semiconductor fins

Abstract

An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device comprising:
 a plurality of fins having parallel lengths extending in a horizontal direction, the plurality of fins comprising a first fin and a second fin which are separated from each other by an isolation region; and   the isolation region comprising a first portion proximate to the first fin, a second portion proximate to the second fin, and a third portion disposed between the first portion and the second portion, wherein   the first and second portions each comprise a liner that comprises (i) a first vertical section immediately adjacent to the respective first or second fin and (ii) a second vertical section adjacent to and in direct contact with the third portion.   
     
     
         22 . The semiconductor device of  claim 21 , wherein:
 each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate; and   at least a portion of the isolation region extends below the horizontal plane.   
     
     
         23 . The semiconductor device of  claim 21 , wherein:
 each of the plurality of fins is disposed at or above a horizontal plane comprising a top surface of a substrate; and   the bottommost surface of the isolation region is disposed at or above the horizontal plane.   
     
     
         24 . The semiconductor device of  claim 21 , wherein:
 each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate;   a recessed fin is disposed between the first and second fins;   the third portion of the isolation region is disposed over the recessed fin; and   a top surface of the recessed fin is above the horizontal plane.   
     
     
         25 . The semiconductor device of  claim 21 , further comprising:
 a gate structure formed over the first and second fins.   
     
     
         26 . The semiconductor device of  claim 21 , wherein an upper surface of the third portion is substantially coplanar with an upper surface of the first portion. 
     
     
         27 . The semiconductor device of  claim 21 , wherein an upper surface of the third portion is substantially coplanar with upper surfaces of the first and second portions. 
     
     
         28 . The semiconductor device of  claim 21 , wherein the liners comprise a dielectric metal oxide. 
     
     
         29 . The semiconductor device of  claim 21 , wherein the liners comprise a silicon nitride. 
     
     
         30 . The semiconductor device of  claim 21 , wherein the liners each have a thickness of less than about 5 nm. 
     
     
         31 . The semiconductor device of  claim 21 , wherein a width of at least a portion of the first fin is substantially the same as a width of the third portion of the isolation region. 
     
     
         32 . The semiconductor device of  claim 21 , wherein the liners of the first and second portions comprise a discontinuous dielectric material liner disposed between the first and second fins. 
     
     
         33 . A semiconductor device comprising:
 a plurality of fins having parallel lengths extending in a first horizontal direction, the plurality of fins comprising a first fin, a second fin adjacent to the first fin, a third fin adjacent to the second fin, and a fourth fin adjacent to the third fin, wherein   a center-to-center distance between the second and third fins is about 2 times a center-to-center distance between the first and second fins;   the first fin comprises an inward-facing side that faces the second fin;   the second fin comprises an inward-facing side that faces the third fin and an opposite outward-facing side that faces the first fin;   the third fin comprises an inward-facing side that faces the second fin and an opposite outward-facing side that faces the fourth fin;   the fourth fin comprises an inward-facing side that faces the third fin;   the inward-facing sides of the second and third fins are separated from each other by a first isolation region comprising a first portion proximate to the second fin, a second portion proximate to the third fin, and a third portion disposed between the first portion and the second portion; and   the first and second portions each comprise a liner that comprises (i) a vertical section disposed on the inward-facing side of the second or third fin and (ii) a vertical section adjacent to and in direct contact with the third portion.   
     
     
         34 . The semiconductor device of  claim 33 , further comprising:
 second isolation regions disposed between the (iii) outward-facing side of the second fin and the inward-facing side of the first fin, and (iv) between the outward-facing side of the third fin and the inward-facing side of the fourth fin, wherein   the second isolation regions each comprise a liner that comprises (v) a vertical section disposed on the inward-facing side of the first or fourth fin, and (vi) a vertical section disposed on the outward-facing side of the second or third fin.   
     
     
         35 . The semiconductor device of  claim 33 , wherein:
 each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate; and   at least a portion of the first isolation region extends below the horizontal plane.   
     
     
         36 . The semiconductor device of  claim 33 , wherein:
 each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate; and   the bottommost surface of the first isolation region is disposed at or above the horizontal plane.   
     
     
         37 . The semiconductor device of  claim 33 , wherein:
 each of the plurality of fins extends above a horizontal plane comprising a top surface of a substrate;   a recessed fin is disposed between the second and third fins;   the third portion of the first isolation region is disposed over the recessed fin; and   a top surface of the recessed fin is above the horizontal plane.   
     
     
         38 . The semiconductor device of  claim 33 , further comprising:
 a gate structure formed over the plurality of fins and the first and second isolation regions.   
     
     
         39 . The semiconductor device of  claim 33 , wherein an upper surface of the third portion is substantially coplanar with an upper surface of the first portion. 
     
     
         40 . The semiconductor device of  claim 33 , wherein an upper surface of the third portion is substantially coplanar with upper surfaces of the first and second portions. 
     
     
         41 . The semiconductor device of  claim 33 , wherein the liners comprise a dielectric metal oxide. 
     
     
         42 . The semiconductor device of  claim 33 , wherein the liners comprise a silicon nitride. 
     
     
         43 . The semiconductor device of  claim 33 , wherein the liners each have a thickness of less than about 5 nm. 
     
     
         44 . The semiconductor device of  claim 33 , wherein a width of at least a portion of the second fin is substantially the same as a width of the third portion of the first isolation region. 
     
     
         45 . The semiconductor device of  claim 33 , wherein the liners of the first and second portions comprise a discontinuous dielectric material liner disposed between the second and third fins.