System, Semiconductor Device and Method

Abstract

Systems and methods are described herein for the variable and dynamic control of a variable aperture masking unit to define, isolate and/or mask diffusion areas for dopant implantation and/or thermal annealing processes useful in wafer fabrication in the production of advanced semiconductor devices. A plurality of isolation material panels can be dynamically positioned to define a size, position and shape of a variable mask aperture between edges of the plurality of isolation material panels. The isolation material panels are connected between cooperating pairs of carriers that are coupled to and travel along a set of parallel tracks on opposite sides of the variable aperture masking unit.

What is claimed is: 
     
         1 . A semiconductor manufacturing device comprising:
 a plurality of tracks;   a plurality of carriers arranged on corresponding tracks of the plurality of tracks, each of the plurality of carriers being controllable to travel to a specified location along the plurality of tracks;   a plurality of isolation panels coupled to the plurality of carriers with an aperture defined between edges of the plurality of isolation panels;   an aperture control unit to control a desired size of the aperture; and   a semiconductor wafer holding apparatus.   
     
     
         2 . The semiconductor manufacturing device of  claim 1 , wherein the carriers comprise DC/AC motors. 
     
     
         3 . The semiconductor manufacturing device of  claim 1 , wherein the plurality of isolation panels comprises quartz. 
     
     
         4 . The semiconductor manufacturing device of  claim 1 , wherein the plurality of isolation panels comprises graphite. 
     
     
         5 . The semiconductor manufacturing device of  claim 1 , wherein each isolation panel of the plurality of isolation panels spans between and is held in position by a coordinated pair of the plurality of carriers coupled to a pair of the plurality of tracks on opposing sides of the semiconductor manufacturing device. 
     
     
         6 . The semiconductor manufacturing device of  claim 5 , wherein a first set of the isolation panels are held in position by a first set of the coordinated pairs of carriers, the first set of the coordinated pairs of carriers being coupled to a first pair of tracks on opposing sides of the apparatus, and wherein a second set of isolation panels are held in position by a second set of the coordinated pairs of carriers, the second set of the coordinated pairs of carriers being coupled to a second pair of tracks on opposing sides of the apparatus, the second pair of tracks on opposing sides of the apparatus being arranged in a direction perpendicular to the first pair of tracks on opposing sides of the apparatus. 
     
     
         7 . The semiconductor manufacturing device of  claim 6 , wherein the first set of isolation panels is separated from the second set of isolation panels by a first distance greater than zero. 
     
     
         8 . A method of manufacturing a semiconductor device, the method comprising:
 placing a semiconductor substrate into a manufacturing device, the manufacturing device comprising:
 a plurality of tracks; 
 a plurality of carriers arranged on corresponding tracks of the plurality of tracks, each of the plurality of carriers being controllable to travel to a specified location along a track of the plurality of tracks; 
 a plurality of isolation panels coupled to the plurality of carriers with an aperture defined between edges of the plurality of isolation panels; 
 an aperture control unit to control a desired size of the aperture; and 
 a semiconductor wafer holding apparatus; and 
   introducing a first impurity of a first ion beam into the semiconductor substrate through the aperture.   
     
     
         9 . The method of  claim 8 , wherein the carriers comprise DC/AC motors. 
     
     
         10 . The method of  claim 8 , wherein the plurality of isolation panels comprises quartz. 
     
     
         11 . The method of  claim 8 , wherein the plurality of isolation panels comprises graphite. 
     
     
         12 . The method of  claim 8 , wherein each isolation panel of the plurality of isolation panels spans between and is held in position by a coordinated pair of carriers coupled to a pair of the plurality of tracks on opposing sides of the semiconductor manufacturing device. 
     
     
         13 . A method of manufacturing a semiconductor device, the method comprising:
 moving an isolation panel of a plurality of isolation panels of a variable area masking unit to a first unique position such that a first aperture of the variable area masking unit is defined between edges of the plurality of isolation panels; and   performing a first series of a first dopant implantation process using the first aperture of the variable area masking unit to expose a first implantation area I 1  in a series of target dies on a semiconductor wafer and using the plurality of isolation panels of the variable area masking unit to mask areas of the semiconductor wafer outside of the first implantation area I 1  in the series of target dies.   
     
     
         14 . The method of  claim 13 , further comprising:
 moving the isolation panel of the plurality of isolation panels of the variable area masking unit to a second unique position such that a second aperture of the variable area masking unit is defined between edges of the plurality of isolation panels; and   performing a second series of a second dopant implantation process using the second aperture of the variable area masking unit to expose a second implantation area in the series of target dies on the semiconductor wafer and using the plurality of isolation panels of the variable area masking unit to mask areas of the semiconductor wafer outside of the second implantation area in the series of target dies.   
     
     
         15 . The method of  claim 14 , further comprising:
 moving the isolation panel of the plurality of isolation panels of the variable area masking unit to a third unique position such that a third aperture of the variable area masking unit is defined between edges of the plurality of isolation panels; and   performing a third dopant implantation process using the third aperture of the variable area masking unit to expose a third implantation area on the semiconductor wafer and using the plurality of isolation panels as a mask to block areas of the semiconductor wafer outside of the third implantation area.   
     
     
         16 . The method of  claim 15 , further comprising:
 conducting a first series of movements of the semiconductor wafer to align each of a series of target dies of the semiconductor wafer into a position to receive the first dopant implantation using the first aperture to form an n-well region of a first semiconductor device in each of the series of target dies;   conducting a second series of movements of the semiconductor wafer to arrange and align each of the series of target dies of the semiconductor wafer into a position to receive the second dopant implantation using the second aperture to form an n+ source/drain region of the first semiconductor device in each of the series of target dies; and   conducting a third series of movements of the semiconductor wafer to arrange and align each of the series of target dies into a position to receive the third dopant implantation using the third aperture to form a p+ source/drain region of the first semiconductor device in each of the series of target dies.   
     
     
         17 . The method of  claim 16 , further comprising:
 moving the isolation panel of the plurality of isolation panels of the variable area masking unit to a fourth unique position such that a fourth aperture of the variable area masking unit is defined between edges of the plurality of isolation panels; and   performing a series of fourth dopant implantations using the fourth aperture of the variable area masking unit to form a n+ source/drain region of the first semiconductor device in each of the series of target dies arranged and aligned in the position to receive the second dopant implantation.   
     
     
         18 . The method of  claim 17 , further comprising:
 moving the isolation panel of the plurality of isolation panels of the variable area masking unit to a fifth unique position such that a fifth aperture of the variable area masking unit is defined between edges of the plurality of isolation panels; and   performing a series of fifth dopant implantations using the fifth aperture of the variable area masking unit to form a p+ source/drain region of the first semiconductor device in each of the series of target dies arranged and aligned in the position to receive the third dopant implantation.   
     
     
         19 . The method of  claim 18 , wherein the performing the first dopant implantation process, comprises performing a phosphorus diffusion process, wherein the performing the second dopant implantation process comprises performing an arsenic implantation process, and wherein the performing the third dopant implantation process comprises performing a boron implantation process. 
     
     
         20 . The method of  claim 18 , further comprising:
 moving a second isolation panel of a second plurality of isolation panels of a second variable area masking unit to a second unique position;   directing a laser through the second variable area masking unit; and   annealing the semiconductor wafer with the laser.