Microfluidic chips with one or more vias

Abstract

Microfluidic chips that can comprise thin substrates and/or a high density of vias are described herein. An apparatus comprises: a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer. In some embodiments, the silicon device layer has a thickness between about 7 micrometers and about 500 micrometers while a via of the plurality of vias has a diameter between about 5 micrometers and about 5 millimeters.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a silicon device layer comprising a plurality of vias, the plurality of vias comprising greater than or equal to about 100 vias per square centimeter of a surface of the silicon device layer and less than or equal to about 100,000 vias per square centimeter of the surface of the silicon device layer, and the plurality of vias extending through the silicon device layer; and   a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer.   
     
     
         2 . The apparatus of  claim 1 , wherein the sealing layer is selected from a group consisting of silicon and glass. 
     
     
         3 . The apparatus of  claim 2 , wherein the silicon device layer has a thickness greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers. 
     
     
         4 . The apparatus of  claim 2 , wherein a via of the plurality of vias has a diameter greater than or equal to about 5 micrometers and less than or equal to about 5 millimeters. 
     
     
         5 . The apparatus of  claim 1 , further comprising a microfluidic element located on a second surface of the silicon device layer. 
     
     
         6 . The apparatus of  claim 5 , wherein the microfluidic element is in fluid communication with a via of the plurality of vias. 
     
     
         7 . The apparatus of  claim 6 , wherein the microfluidic element is encapsulated by a combination of the silicon device layer and the sealing layer. 
     
     
         8 . The apparatus of  claim 5 , wherein the microfluidic element is selected from a group consisting of a deterministic displacement array and a condenser array. 
     
     
         9 . The apparatus of  claim 8 , further comprising a fluidic bus embedded within the surface of the silicon device layer and in fluid communication with the microfluidic element. 
     
     
         10 . The apparatus of  claim 1 , wherein the sealing layer is thicker than the silicon device layer. 
     
     
         11 . An apparatus, comprising:
 a silicon device layer comprising a via and a microfluidic device, the via extending through the silicon device layer and in fluid communication with the microfluidic device, wherein the silicon device layer has a thickness greater than or equal to about 7 micrometers and less than or equal to about 500 micrometers; and   a sealing layer bonded to the silicon device layer, wherein the sealing layer has greater rigidity than the silicon device layer.   
     
     
         12 . The apparatus of  claim 11 , wherein the sealing layer has a second thickness greater than or equal to about 100 micrometers and less than or equal to about 2.5 millimeters. 
     
     
         13 . The apparatus of  claim 11 , wherein the sealing layer is selected from a group consisting of silicon and glass. 
     
     
         14 . The apparatus of  claim 11 , wherein the via has a diameter greater than or equal to about 5 micrometers and less than or equal to about 5 millimeters. 
     
     
         15 . The apparatus of  claim 11 , wherein the via is comprised within a plurality of vias. 
     
     
         16 . The apparatus of  claim 15 , wherein the plurality of vias comprise greater than or equal to about 100 vias and less than or equal to about 100,000 vias per square centimeter of a surface of the silicon device layer opposite to the sealing layer.