Sic super junction trench mosfet

Abstract

A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

1 - 7 . (canceled) 
     
     
         8 . A method for manufacturing a SiC power device comprising steps of:
 growing an epitaxial layer of a first conductivity type onto a substrate of said first conductivity type, wherein said epitaxial layer has a lower doping concentration than the substrate;   forming a plurality of first type and second type gate trenches by performing following steps:   a) forming a trench mask onto a top surface of said epitaxial layer for definition of the plurality of first type gate trenches;   b) forming said first type gate trenches in said epitaxial layer by etching through open regions in said trench mask;   c) forming a dielectric layer on sidewalls and bottoms of said plurality of first type gate trenches;   d) removing said dielectric layer on bottoms of said first type gate trenches by an anisotropic oxide etch;   e) performing an anisotropic silicon etch to form a plurality of second type gate trenches.   
     
     
         9 . The method of  claim 8 , further carrying out an angle ion implantation of said second conductivity type dopant into said sidewalls and bottoms of said plurality of second type gate trenches to form a second conductivity type doped region surrounding each of said plurality of second type gate trenches. 
     
     
         10 . The method of  claim 9 , further comprising a zero degree ion implantation of said second conductivity type dopant. 
     
     
         11 . The method of  claim 8 , further depositing a Boron Silicate Glass (BSG) layer into said plurality of second type gate trenches after formation of said plurality of second gate type trenches to form a second conductivity type doped region surrounding sidewalls and bottoms of said plurality of second type gate trenches. 
     
     
         12 . The method of  claim 8 , further comprising the steps of:
 forming a first insulating film along inner surfaces of said plurality of first type and inside said plurality of second type gate trenches, wherein said plurality of second type gate trenches filled up by said first insulation film;   etching back said first insulating film from upper portion of said plurality of first type gate trenches to remove said first insulating film from top surface of said epitaxial layer and sidewalls of said plurality of first type gate trenches;   forming a second insulating film as a gate oxide layer on sidewalls of said plurality of first type gate trenches;   depositing a doped poly-silicon layer into said plurality of first type gate trenches; and   etching back said first doped poly-silicon to form a gate electrode.