US2023041977A1PendingUtilityA1

3d heterogeneous integrations and methods of making thereof

Assignee: BROADPAK CORPPriority: May 20, 2015Filed: Oct 17, 2022Published: Feb 9, 2023
Est. expiryMay 20, 2035(~8.8 yrs left)· nominal 20-yr term from priority
Inventors:Farhang Yazdani
H10W 70/682H10W 70/63H10W 90/288H10W 70/60H10W 90/297H10W 90/22H10W 90/24H10W 72/823H10W 90/722H10W 72/01H10W 72/884H10W 90/754H10W 90/724H10W 72/252H10W 90/732H10W 44/20H10W 42/40H10W 90/401H10W 70/611H10W 70/685H10W 90/701H10W 40/43H10W 40/10H10W 70/68H10W 70/698H10W 90/00H10W 90/752H10W 90/291H10W 72/20H10W 76/12H10W 74/111H10W 72/071H10W 70/635H10W 70/095H10W 70/65Y10T29/53183Y10T29/53174Y10T29/53178H01L 23/49827H01L 23/573H01L 23/49838H01L 2225/06513H01L 25/105H01L 24/13H01L 25/0657H01L 21/52H01L 2225/06527H01L 2225/06572H01L 2924/19041H01L 2224/48227H01L 24/16H01L 25/18H01L 2224/48091H01L 2224/13147H01L 23/147H01L 25/0652H01L 2225/1082H01L 23/36H01L 2924/19107H01L 2924/00014H01L 21/486H01L 2924/15192H01L 23/3107H01L 23/5383H01L 2225/1041H01L 2224/45015H01L 23/49816H01L 2924/14H01L 25/50H01L 23/04H01L 24/48H01L 23/49833H01L 2924/30107H01L 23/66H01L 2224/13101H01L 2225/06517H01L 23/467H01L 2225/1094H01L 2225/1052H01L 2225/06548H01L 2924/10253H01L 23/5385H01L 2225/06541H01L 23/13
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Claims

Abstract

An integrated circuit package comprising one or more electronic component(s); a first substrate including a first surface and a second surface of the first substrate; and a second substrate including a first surface and a second surface of the second substrate. The first substrate including a first first-substrate cavity on the first surface of the first substrate. The second substrate includes a first second-substrate cavity on the first surface of the second substrate. The second surface of the first substrate and the second surface of the second substrate is located between the first surface of the first substrate and the first surface of the second substrate; or the first surface of the first substrate and the first surface of the second substrate is located between the second surface of the first substrate and the second surface of the second substrate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An integrated circuit package comprising:
 one or more component(s); and   one or more substrate(s), wherein   said one or more substrate(s) including a first substrate and a second substrate,   said first substrate including a first surface of said first substrate and a second surface of said first substrate,   said second substrate including a first surface of said second substrate and a second surface of said second substrate,   said first substrate including a first first-substrate cavity on the first surface of said first substrate,   said second substrate includes a first second-substrate cavity on the first surface of said second substrate,   said second surface of said first substrate and said second surface of said second substrate is located between said first surface of said first substrate and the first surface of said second substrate, and   said one or more component(s) is/are disposed inside said first first-substrate cavity of first substrate and/or said first second-substrate cavity of second substrate.   
     
     
         2 . The integrated circuit package according to  claim 1 , wherein
 one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wirebond method or a waveguide.   
     
     
         3 . The integrated circuit package according to  claim 1 , wherein
 said one or more substrate(s) comprises of waveguide(s) and/or nanowires.   
     
     
         4 . The integrated circuit package according to  claim 1 , wherein
 one of said one or more component(s) is a power management/regulator or power device or security sub-circuit or tamper detect circuit or router or switch or antenna or radar or phased array or modem or baseband or transceiver or mm-wave subsystem or silicon-on-insulator or amplifier or Field Programmable Gate Array (FPGA) or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or micro LED or Application-Specific Integrated Circuit (ASIC) or Through-Silicon Via (TSV) or laser or analog circuit or digital circuit or Serializer/Deserializer (SerDes) or filter or Lens or Graphics Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy mold compound (EMC) or under-fill material or heat-pipe or mirror or fan or bump or fiber or accelerator/co-processor or processor core or nanowire or Microelectromechanical Systems (MEMS) or membrane or heat spreader or energy source or sensing material or piezoelectric or light source or touch screen or display or Liquid Crystal Display (LCD) or organic light-emitting diode (OLED) or battery or Electromagnetic Shield (EMI) coating.   
     
     
         5 . The integrated circuit package according to  claim 1 , wherein
 one of said one or more component(s) is/are stacked component(s).   
     
     
         6 . The integrated circuit package according to  claim 1 , wherein
 one of said one or more substrate(s) is a semiconductor.   
     
     
         7 . An integrated circuit package comprising:
 one or more component(s); and   one or more substrate(s), wherein   said one or more substrate(s) including a first substrate and a second substrate,   said first substrate including a first surface of said first substrate and a second surface of said first substrate,   said second substrate including a first surface of said second substrate and a second surface of said second substrate,   said first substrate including a first first-substrate cavity on the first surface of said first substrate,   said second substrate includes a first second-substrate cavity on the first surface of said second substrate,   said first surface of said first substrate and the first surface of said second substrate is located between said second surface of said first substrate and said second surface of said second substrate, and   said one or more component(s) is/are disposed inside said first first-substrate cavity of first substrate and/or said first second-substrate cavity of second substrate.   
     
     
         8 . The integrated circuit package according to  claim 7 , wherein
 one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wirebond method or a waveguide.   
     
     
         9 . The integrated circuit package according to  claim 7 , wherein
 said one or more substrate(s) comprises of waveguide(s) and/or nanowires.   
     
     
         10 . The integrated circuit package according to  claim 7 , wherein
 one of said one or more component(s) is a power management/regulator or power device or security sub-circuit or tamper detect circuit or router or switch or antenna or radar or phased array or modem or baseband or transceiver or mm-wave subsystem or silicon-on-insulator or amplifier or Field Programmable Gate Array (FPGA) or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or micro LED or Application-Specific Integrated Circuit (ASIC) or Through-Silicon Via (TSV) or laser or analog circuit or digital circuit or Serializer/Deserializer (SerDes) or filter or Lens or Graphics Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy mold compound (EMC) or under-fill material or heat-pipe or mirror or fan or bump or fiber or accelerator/co-processor or processor core or nanowire or Microelectromechanical Systems (MEMS) or membrane or heat spreader or energy source or sensing material or piezoelectric or light source or touch screen or display or Liquid Crystal Display (LCD) or organic light-emitting diode (OLED) or battery or Electromagnetic Shield (EMI) coating.   
     
     
         11 . The integrated circuit package according to  claim 7 , wherein
 one of said component(s) is/are stacked component(s).   
     
     
         12 . The integrated circuit package according to  claim 7 , wherein
 one of said one or more substrate(s) is a semiconductor.   
     
     
         13 . An integrated circuit package comprising:
 one or more component(s); and   one or more substrate(s), wherein   said one or more substrate(s) including a first substrate, a second substrate and a third substrate, wherein   said first substrate including a first surface of said first substrate and a second surface of said first substrate,   said second substrate including a first surface of said second substrate and a second surface of said second substrate,   said first substrate including a first first-substrate cavity on the first surface of said first substrate,   said second substrate includes a first second-substrate cavity on the first surface of said second substrate,   said first surface of said first substrate and the first surface of said second substrate is located between said second surface of said first substrate and said second surface of said second substrate,   
       said third substrate is coupled to said first substrate and/or said second substrate, and
 said one or more component(s) is/are disposed inside said first first-substrate cavity of first substrate and/or said first second-substrate cavity of second substrate. 
 
     
     
         14 . The integrated circuit package according to  claim 13 , wherein
 one of said one or more component(s) is electrically and/or optically coupled to said one or more substrate(s) using a flip chip or a wirebond method or a waveguide.   
     
     
         15 . The integrated circuit package according to  claim 13 , wherein
 said one or more substrate(s) comprises of waveguide(s) and/or nanowires.   
     
     
         16 . The integrated circuit package according to  claim 13 , wherein
 one of said one or more substrate(s) is a semiconductor.   
     
     
         17 . The integrated circuit package according to  claim 13 , wherein
 one of said one or more component(s) is a power management/regulator or power device or security sub-circuit or tamper detect circuit or router or switch or antenna or radar or phased array or modem or baseband or transceiver or mm-wave subsystem or silicon-on-insulator or amplifier or Field Programmable Gate Array (FPGA) or capacitor or resistor or inductor or processor or memory or sensor or analog-to-digital converter or digital-to-analog converter or electrical-optical converter or optical-electrical converter or Light Emitting Diode (LED) or micro LED or Application-Specific Integrated Circuit (ASIC) or Through-Silicon Via (TSV) or laser or analog circuit or digital circuit or Serializer/Deserializer (SerDes) or filter or Lens or Graphics Processing Unit (GPU) or magnet or waveguide or wirebond or epoxy mold compound (EMC) or under-fill material or heat-pipe or mirror or fan or bump or fiber or accelerator/co-processor or processor core or nanowire or Microelectromechanical Systems (MEMS) or membrane or heat spreader or energy source or sensing material or piezoelectric or light source or touch screen or display or Liquid Crystal Display (LCD) or organic light-emitting diode (OLED) or battery or Electromagnetic Shield (EMI) coating.   
     
     
         18 . The integrated circuit package according to  claim 13 , wherein
 one of said component(s) is/are stacked component(s).   
     
     
         19 . The integrated circuit package according to  claim 13 , wherein
 one or more nanowire is coupled to said component(s) and/or said substrate(s) and/or said cavity(ies).   
     
     
         20 . The integrated circuit package according to  claim 7 , wherein
 one or more nanowire is coupled to said component(s) and/or said substrate(s) and/or said cavity(ies).

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