Device having cell that includes extended active region

Abstract

A device includes a single standard cell. The single standard cell includes a first transistor region including a first extended active region extending between a first side cell boundary and a second side cell boundary opposite the first side cell boundary, and includes a plurality of source regions and one drain region. The single standard cell further includes a second transistor region including a second extended active region extending between the first side cell boundary and the second side cell boundary, and includes a source region and a single drain region.

1 . A device, the device comprising:
 a single standard cell comprising:
 a first transistor region including a first extended active region extending between a first side cell boundary and a second side cell boundary opposite the first side cell boundary, and comprising a plurality of source regions and one drain region; 
 a second transistor region including a second extended active region extending between the first side cell boundary and the second side cell boundary, and comprising a source region and a single drain region; and 
 a first active gate strip extending over the first extended active region and the second extended active region. 
   
     
     
         2 . The device of  claim 1 , wherein the one drain region is electrically connected to the single drain region. 
     
     
         3 . The device of  claim 1 , wherein the first side cell boundary is spaced from the second side cell boundary in a first direction, and the one drain region is offset from the single drain region in first direction. 
     
     
         4 . The device of  claim 1 , further comprising a dummy gate strip extending across the first extended active region and the second extended active region. 
     
     
         5 . The device of  claim 4 , wherein the single drain region is between the dummy gate strip and the second side cell boundary. 
     
     
         6 . The device of  claim 4 , wherein the one drain region is between the dummy gate strip and the first side cell boundary. 
     
     
         7 . The device of  claim 1 , further comprising a second active gate strip extending across the first extended active region and the second extended active region. 
     
     
         8 . The device of  claim 1 , wherein a first source region of the plurality of source regions is between the first active gate strip and the first side cell boundary. 
     
     
         9 . The device of  claim 1 , wherein the source region is between the first active gate strip and the second side cell boundary. 
     
     
         10 . A device, the device comprising:
 a single standard cell comprising:
 a first transistor region including a first extended active region extending between a first side cell boundary and a second side cell boundary opposite the first side cell boundary, and comprising a plurality of source regions and one drain region; 
 a second transistor region including a second extended active region extending between the first side cell boundary and the second side cell boundary, and comprising a source region and a single drain region; 
 a plurality of gate structures extending across the first extended active region and the second extended active region; and 
 a dummy gate structure extending across the first extended active region and the second extended active region. 
   
     
     
         11 . The device of  claim 10 , wherein a first gate structure of the plurality of gate structures is between the dummy gate structure and a second gate structure of the plurality of gate structures. 
     
     
         12 . The device of  claim 10 , wherein the one drain region is between the dummy gate structure and the plurality of gate structures. 
     
     
         13 . The device of  claim 10 , wherein the dummy gate structure is between the plurality of gate structures and the single drain region. 
     
     
         14 . The device of  claim 10 , wherein the one drain region is electrically connected to the single drain region. 
     
     
         15 . The device of  claim 10 , wherein a first source region of the plurality of source regions is between the dummy gate structure and the second side cell boundary. 
     
     
         16 . A device, the device comprising:
 a single standard cell comprising:
 a first transistor region including a first extended active region extending from a first side cell boundary to a second side cell boundary opposite the first side cell boundary, and comprising a plurality of source regions and one drain region; and 
 a second transistor region including a second extended active region extending from the first side cell boundary to the second side cell boundary, and comprising a single source region and a single drain region. 
   
     
     
         17 . The device of  claim 16 , wherein the first extended active region is spaced from the second extended active region in a first direction, and the one drain region is offset from the single drain region in a second direction perpendicular to the first direction. 
     
     
         18 . The device of  claim 16 , further comprising a plurality of dummy gate strips. 
     
     
         19 . The device of  claim 18 , wherein the single drain region is between a first dummy gate strip of the plurality of dummy gate strips and a second dummy gate strip of the plurality of dummy gate strips. 
     
     
         20 . The device of  claim 19 , wherein each of the first dummy gate strip and the second dummy gate strip extends across the first extended active region and the second extended active region.