Sonos ono stack scaling

Abstract

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

What is claimed is: 
     
         1 . A non-volatile memory device comprising:
 a channel region formed from a semiconductor material;   a tunnelling layer abutting the channel region;   a charge-trapping layer abutting the tunnelling layer; and   a blocking layer abutting the charge-trapping layer, wherein the tunnelling layer includes a nitridized oxide.   
     
     
         2 . The device of  claim 1 , wherein the tunneling layer includes a first region proximate to the channel region and a second region proximate the charge trapping layer, wherein the first layer includes the nitridized oxide. 
     
     
         3 . The device of  claim 2 , wherein the charge-trapping layer comprises at least a first nitride layer proximate to the tunneling layer and a second nitride layer away from the tunnelling layer. 
     
     
         4 . The device of  claim 3 , wherein the first and second nitride layers comprise oxynitride. 
     
     
         5 . The device of  claim 3 , the first nitride layer is oxygen rich relative to the second nitride layer. 
     
     
         6 . The device of  claim 1 , further including a gate layer abutting the blocking layer. 
     
     
         7 . The device of  claim 6 , wherein the device is manufactured using a gate last scheme. 
     
     
         8 . The device of  claim 6 , wherein the device is a gate all around structure. 
     
     
         9 . The device of  claim 8 , further including an annular channel region. 
     
     
         10 . The device of  claim 5 , wherein the charge trapping layer is a multi-layer charge trapping layer including an intermediate anti-tunneling layer separating an oxygen-lean second layer from the oxygen-rich first nitride layer. 
     
     
         11 . A nonvolatile trapped-charge memory device comprising:
 a channel region formed from a semiconductor material;   a tunneling layer abutting the channel region, wherein the tunnelling layer includes a nitridized oxide;   a multi-layer charge trapping layer overlying the tunneling layer; and   a blocking layer overlying the multi-layer charge trapping layer.   
     
     
         12 . The device of  claim 11 , wherein the charge trapping layer is a multi-layer charge trapping layer wherein the multi-layer charge-trapping layer comprises at least a first layer proximate to the tunneling layer and a second layer away from the tunnelling layer wherein the first layer is oxygen-rich and the second layer is oxygen-lean. 
     
     
         13 . The device of  claim 12 , wherein the first and second layer of the multi-layer charge trapping layer are nitrides. 
     
     
         14 . The device of  claim 12 , wherein the tunneling layer includes a first region proximate to the channel region and a second region proximate the charge trapping layer, wherein the first layer includes the nitridized oxide. 
     
     
         15 . The device of  claim 12 , further including a gate layer abutting the blocking layer. 
     
     
         16 . The device of  claim 15 , wherein the device is manufactured using a gate last scheme. 
     
     
         17 . The device of  claim 15 , wherein the device is a gate all around structure. 
     
     
         18 . The device of  claim 17 , further including an annular channel region. 
     
     
         19 . The device of  claim 12 , further including an intermediate anti-tunneling layer separating then oxygen-lean second layer from the oxygen-rich first layer.