Branch type logging in last branch registers

Abstract

A processor includes a counter to store a cycle count that tracks a number of cycles between retirement of a first branch instruction and retirement of a second branch instruction during execution of a set of instructions. The processor further includes a stack of registers coupled to the counter, wherein the stack of registers is to store branch type information including: a first value of the counter when the first branch instruction is retired; a second value of the counter when the second branch instruction is retired; a first type information value indicating a type of the first branch instruction; and a second type information value indicating a type of the second branch instruction.

What is claimed is: 
     
         1 . A processor comprising:
 decode circuitry to decode a plurality of branch instructions, including a first branch instruction and a second branch instruction;   execution circuitry coupled to the decode circuitry, the execution circuitry to execute the plurality of branch instructions, including the first branch instruction and the second branch instruction; and   a plurality of registers to store branch information about the plurality of branch instructions, the plurality of registers including a first register to store branch information about the first branch instruction, and a second register to store branch information about the second branch instruction, the first register to include:
 a counter field to store a number of clock cycles since branch information was provided for a branch instruction immediately prior to the first branch instruction; 
 a type field to store branch type information to indicate a branch type of the first branch instruction; 
 a misprediction field to store branch prediction information about the first branch instruction; and 
 a transaction field to store information to indicate whether the first branch instruction is in a transactional region. 
   
     
     
         2 . The processor of  claim 1 , wherein the type field is to store the branch type information to indicate any one of at least seven different branch types for the first branch instruction. 
     
     
         3 . The processor of  claim 2 , wherein the at least seven different branch types include at least a conditional type, an unconditional type, an indirect type, a direct type, a call type, and a return type. 
     
     
         4 . The processor of  claim 1 , wherein the first register is a 64-bit register. 
     
     
         5 . The processor of  claim 1 , wherein the type field comprises 4 bits. 
     
     
         6 . The processor of  claim 1 , wherein the transaction field is a 1-bit field. 
     
     
         7 . The processor of  claim 1 , wherein the misprediction field is a 1-bit field. 
     
     
         8 . The processor of  claim 1 , wherein the branch prediction information is to indicate whether a branch of the first branch instruction was mispredicted. 
     
     
         9 . The processor of  claim 1 , wherein the first register further includes an abort field to store abort information associated with the first branch instruction. 
     
     
         10 . The processor of  claim 9 , wherein the abort field is a 1-bit field. 
     
     
         11 . The processor of  claim 1 , wherein the plurality of registers are also to store:
 a source address for the first branch instruction; and   a target address for first the branch instruction.   
     
     
         12 . The processor of  claim 1 , further comprising a counter to count the number of clock cycles. 
     
     
         13 . The processor of  claim 1 , wherein the first register further comprises a plurality of additional fields to store additional information associated with the first branch instruction. 
     
     
         14 . A system on a chip (SoC) comprising:
 a memory controller; and   a processor coupled with the memory controller, the processor comprising:
 decode circuitry to decode a plurality of branch instructions, including a first branch instruction and a second branch instruction; 
 execution circuitry coupled to the decode circuitry, the execution circuitry to execute the plurality of branch instructions, including the first branch instruction and the second branch instruction; and 
 a plurality of registers to store branch information about the plurality of branch instructions, the plurality of registers including a first register to store branch information about the first branch instruction, and a second register to store branch information about the second branch instruction, the first register to include:
 a counter field to store a number of clock cycles since branch information was provided for a branch instruction immediately prior to the first branch instruction; 
 a type field to store branch type information to indicate a branch type of the first branch instruction; 
 a misprediction field to store branch prediction information about the first branch instruction; and 
 a transaction field to store information to indicate whether the first branch instruction is in a transactional region. 
 
   
     
     
         15 . The SoC of  claim 14 , wherein the type field is to store the branch type information to indicate any one of at least seven different branch types for the first branch instruction, and wherein the SoC further comprises a graphics logic coupled with the processor. 
     
     
         16 . The SoC of  claim 15 , wherein the at least seven different branch types include at least a conditional type, an unconditional type, an indirect type, a direct type, a call type, and a return type, and wherein the SoC further comprises an image processor coupled with the processor. 
     
     
         17 . The SoC of  claim 14 , wherein the first register is a 64-bit register, wherein the type field comprises 4 bits, wherein the transaction field is a 1-bit field, wherein the misprediction field is a 1-bit field, and wherein the SoC further comprises an audio processor coupled with the processor. 
     
     
         18 . The SoC of  claim 14 , wherein the first register further includes an abort field to store abort information associated with the first branch instruction, wherein the abort field is a 1-bit field, and wherein the SoC further comprises a display unit coupled with the processor. 
     
     
         19 . A system comprising:
 a system memory; and   a processor coupled with the system memory, the processor comprising:   decode circuitry to decode a plurality of branch instructions, including a first branch instruction and a second branch instruction;   execution circuitry coupled to the decode circuitry, the execution circuitry to execute the plurality of branch instructions, including the first branch instruction and the second branch instruction; and   a plurality of registers to store branch information about the plurality of branch instructions, the plurality of registers including a first register to store branch information about the first branch instruction, and a second register to store branch information about the second branch instruction, the first register to include:
 a counter field to store a number of clock cycles since branch information was provided for a branch instruction immediately prior to the first branch instruction; 
 a type field to store branch type information to indicate a branch type of the first branch instruction; 
 a misprediction field to store branch prediction information about the first branch instruction; and 
 a transaction field to store information to indicate whether the first branch instruction is in a transactional region. 
   
     
     
         20 . The system of  claim 19 , wherein the type field is to store the branch type information to indicate any one of at least seven different branch types for the first branch instruction, and wherein the system further comprises a mass storage device coupled with the processor. 
     
     
         21 . The system of  claim 20 , wherein the at least seven different branch types include at least a conditional type, an unconditional type, an indirect type, a direct type, a call type, and a return type, and wherein the mass storage device comprises a disk drive. 
     
     
         22 . The system of  claim 19 , wherein the first register is a 64-bit register, wherein the type field comprises 4 bits, wherein the transaction field is a 1-bit field, wherein the misprediction field is a 1-bit field, and wherein the first register further includes an abort field to store abort information associated with the first branch instruction, wherein the abort field is a 1-bit field, and wherein the system further comprises a communication device coupled with the processor.