US2023101233A1PendingUtilityA1

Semiconductor device and method for fabricating the same

Assignee: UNITED MICROELECTRONICS CORPPriority: Apr 16, 2020Filed: Dec 5, 2022Published: Mar 30, 2023
Est. expiryApr 16, 2040(~13.7 yrs left)· nominal 20-yr term from priority
H10W 20/037H10N 50/10G11C 11/161H10B 61/00H10N 50/80H10N 50/01H01L 27/222H01L 43/02H01L 43/12
71
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method for fabricating a semiconductor device, comprising:
 forming a first metal interconnection on a substrate;   forming a stop layer on the first metal interconnection;   removing the stop layer to form a first opening;   forming an electromigration enhancing layer in the first opening; and   forming a second metal interconnection on the electromigration enhancing layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a first inter-metal dielectric (IMD) layer on the substrate;   forming the first metal interconnection in the first IMD layer;   forming the stop layer on the first IMD layer;   forming the electromigration enhancing layer in the first opening;   forming a second IMD layer on the stop layer and the electromigration enhancing layer;   forming the second metal interconnection on the electromigration enhancing layer; and   forming a first magnetic tunneling junction (MTJ) on the second metal interconnection.   
     
     
         3 . The method of  claim 2 , further comprising planarizing the electromigration enhancing layer before forming the second IMD layer. 
     
     
         4 . The method of  claim 2 , further comprising:
 forming the second metal interconnection and a third metal interconnection on the electromigration enhancing layer; and   forming the first MTJ on the second metal interconnection and a second MTJ on the third metal interconnection.   
     
     
         5 . The method of  claim 4 , further comprising:
 removing the stop layer to form the first opening and a second opening;   forming the electromigration enhancing layer in the first opening and the second opening;   planarizing the electromigration enhancing layer to form a first electromigration enhancing layer and a second electromigration enhancing layer; and   forming the second metal interconnection on the first electromigration enhancing layer and the third metal interconnection on the second electromigration enhancing layer.   
     
     
         6 . The method of  claim 1 , wherein the first metal interconnection and the second metal interconnection comprise different materials. 
     
     
         7 . The method of  claim 1 , wherein the first metal interconnection and the electromigration enhancing layer comprise different materials. 
     
     
         8 . The method of  claim 1 , wherein the second metal interconnection and the electromigration enhancing layer comprise different materials.

Join the waitlist — get patent alerts

Track US2023101233A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.