US2023106156A1PendingUtilityA1
Semiconductor device and method for fabricating the same
Assignee: UNITED MICROELECTRONICS CORPPriority: Apr 16, 2020Filed: Dec 5, 2022Published: Apr 6, 2023
Est. expiryApr 16, 2040(~13.7 yrs left)· nominal 20-yr term from priority
H10W 20/037H10N 50/10H10N 50/01H10B 61/00H10N 50/80G11C 11/161H01L 27/222H01L 43/12H01L 43/02
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Claims
Abstract
A semiconductor device includes a first metal interconnection on a substrate, a first inter-metal dielectric (IMD) layer around the first metal interconnection, an electromigration enhancing layer on the first metal interconnection, a second IMD layer on and around the electromigration enhancing layer, and a second metal interconnection on the electromigration enhancing layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device, comprising:
a first metal interconnection on a substrate; a first inter-metal dielectric (IMD) layer around the first metal interconnection; an electromigration enhancing layer on the first metal interconnection; a second IMD layer on and around the electromigration enhancing layer; and a second metal interconnection on the electromigration enhancing layer.
2 . The semiconductor device of claim 1 , further comprising:
a third metal interconnection on the electromigration enhancing layer; the second IMD layer around the second metal interconnection and the third metal interconnection; a first magnetic tunneling junction (MTJ) on the second metal interconnection; and a second MTJ on the third metal interconnection.
3 . The semiconductor device of claim 1 , where bottom surfaces of the electromigration enhancing layer and the second IMD layer are coplanar.
4 . The semiconductor device of claim 1 , wherein a sidewall of the electromigration enhancing layer comprises a planar sidewall.
5 . The semiconductor device of claim 1 , wherein a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first IMD layer.
6 . The semiconductor device of claim 1 , wherein a sidewall of the electromigration enhancing layer is orthogonal to a top surface of the first metal interconnection.
7 . The semiconductor device of claim 1 , wherein the first metal interconnection and the second metal interconnection comprise different materials.
8 . The semiconductor device of claim 1 , wherein the first metal interconnection and the electromigration enhancing layer comprise different materials.
9 . The semiconductor device of claim 1 , wherein the second metal interconnection and the electromigration enhancing layer comprise different materials.Join the waitlist — get patent alerts
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