True power shedding apparatus and method to reduce power consumption

Abstract

Described herein are mechanisms and methods for blocking the propagation of signals to Integrated Circuit (IC) components that have been power gated, rather than simply suffering from leakage through signals that might not be parked in a low state. In some embodiments, switches that block the flow of current in such signals may enable turning off power to any IC component and not just to circuits on an IC component that make sole use of protocols that are friendly to power gating. This may advantageously increase power savings, by permitting more portions of a system in an idle state to be power gated, or by reducing or eliminating leakage in signals on boundaries of blocks being power gated, or both.

We claim: 
     
         1 . A method comprising:
 closing a first switchable electrical connection, wherein the first switchable electrical connection carries a supply voltage from an interposer interconnect element to an integrated circuit (IC) component on the interposer interconnect element; and   closing a second switchable electrical connection, wherein the second switchable electrical connection carries a one or more data signal and one or more control signals from the interposer interconnect element to the IC component, and wherein the first switchable electrical connection and the second switchable electrical connection are closed in a sequence such that the first switchable electrical connection is to close before the second switchable electrical connection.   
     
     
         2 . The method of  claim 1 , further comprising:
 opening the first switchable electrical connection and the second switchable electrical connection at substantially a same time.   
     
     
         3 . The method of  claim 1  further comprising:
 programming the interposer interconnect element. 
 
     
     
         4 . The method of  claim 1  further comprising:
 dynamically programming the interposer interconnect element. 
 
     
     
         5 . The method of  claim 1  further comprising:
 closing the first switchable electrical connection after closing the second switchable electrical connection. 
 
     
     
         6 . The method of  claim 1  further comprising:
 closing a third switchable electrical connection, wherein the third switchable electrical connection is to carry from the interposer interconnect element to the IC component a ground voltage. 
 
     
     
         7 . The method of  claim 1  further comprising:
 closing the third switchable electrical connection prior to closing the second switchable electrical connection. 
 
     
     
         8 . The method of  claim 1 , wherein the interposer interconnect element is coupled to a pull-up resistor, which is coupled to a power supply line and a signal interface. 
     
     
         9 . The method of  claim 8 , wherein the power supply line is coupled to the first switchable electrical connection. 
     
     
         10 . The method of  claim 8 , wherein the signal interface is coupled to the second switchable electrical connection. 
     
     
         11 . The method of  claim 8 , wherein the power supply line is coupled to a battery. 
     
     
         12 . An apparatus comprising:
 one or more circuitries coupled to an interposer interconnect element, wherein the one or more circuitries are to provide power supply voltage, ground, and data to an IC component on the interposer interconnect element based, at least in part, on a sequence of operation of the one or more circuitries.   
     
     
         13 . The apparatus of  claim 12 , wherein the one or more circuitries include at least three switches. 
     
     
         14 . The apparatus of  claim 12 , where the one or more circuitries are to provide the ground to the IC component prior to provision of the power supply voltage and the data to the IC component. 
     
     
         15 . The apparatus of  claim 12 , wherein the one or more circuitries are to provide the data to the IC component prior to provision of the power supply voltage to the IC component. 
     
     
         16 . The apparatus of  claim 12 , wherein the one or more circuitries are to discontinue provision of the data and the power supply voltage to the IC component substantially at a same time. 
     
     
         17 . The apparatus of  claim 12 , wherein the one or more circuitries include a pull-up resistor coupled between a supply line that provides the power supply voltage, and a single line that provides the data. 
     
     
         18 . The apparatus of  claim 12 , wherein the interposer interconnect element is dynamically programmable. 
     
     
         19 . A system comprising:
 an interposer interconnect element;   a processor, a radio, a memory, and a sensor on the interposer interconnect element, and   one or more circuitries coupled to an interposer interconnect element, wherein the one or more circuitries are to provide power supply voltage, ground, and data to an IC component on the interposer interconnect element based, at least in part, on a sequence of operation of the one or more circuitries.   
     
     
         20 . The system of  claim 19 , where the one or more circuitries are to provide the ground to the IC component prior to provision of the power supply voltage and the data to the IC component.