Transistor with faceted, raised source/drain region

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to transistors with faceted raised source/drain regions and methods of manufacture. The structure includes: a substrate; a gate structure on the substrate; and faceted, raised source/drain regions adjacent to the gate structure and including at least two different semiconductor materials.

What is claimed: 
     
         1 . A structure comprising:
 a substrate;   a gate structure on the substrate; and   faceted, raised source/drain regions adjacent to the gate structure and comprising at least two different semiconductor materials.   
     
     
         2 . The structure of  claim 1 , wherein the at least two different semiconductor materials comprise epitaxial Si and epitaxial SiGe. 
     
     
         3 . The structure of  claim 1 , wherein the at least two different semiconductor materials comprise an upper semiconductor material, a middle semiconductor material and a lower semiconductor material, and the middle semiconductor material comprises a slower growth rate in a <111> plane than the upper semiconductor material and the lower semiconductor material. 
     
     
         4 . The structure of  claim 3 , wherein the middle semiconductor material comprises a different silicide diffusion rate than the upper semiconductor material. 
     
     
         5 . The structure of  claim 3 , wherein a junction between the middle semiconductor material and the lower semiconductor material prevents diffusion of silicide completely within the lower semiconductor material. 
     
     
         6 . The structure of  claim 3 , wherein the upper semiconductor material and the lower semiconductor material comprise a same semiconductor material and the middle semiconductor material comprises a different semiconductor material. 
     
     
         7 . The structure of  claim 6 , wherein the upper semiconductor material and the lower semiconductor material comprise one of Si, SiC, SiP and SiCP, and the middle semiconductor material comprises SiGe. 
     
     
         8 . The structure of  claim 3 , further comprising silicide on the faceted, raised source/drain regions and the gate structure, wherein the silicide on the faceted, raised source/drain regions comprises a concave profile such that the silicide at a center is farther away from the substrate than at edges. 
     
     
         9 . The structure of  claim 1 , wherein an upper portion of the faceted, raised source/drain regions are remote from sidewalls of the gate structure. 
     
     
         10 . The structure of  claim 1 , wherein the faceted, raised source/drain regions comprise two semiconductor materials with different silicide diffusion rates. 
     
     
         11 . The structure of  claim 10 , wherein the two semiconductor materials comprise an upper semiconductor material comprising SiGe and a lower semiconductor material comprising one of Si, SiC, SiP and SiCP. 
     
     
         12 . A structure comprising:
 a gate structure comprising a silicided region; and   a faceted, raised source/drain regions adjacent to the gate structure, the faceted, raised source/drain regions comprising a stack of epitaxial semiconductor materials and a silicided region partially into the faceted raised source/drain regions.   
     
     
         13 . The structure of  claim 12 , wherein the stack of epitaxial semiconductor material comprises a first semiconductor material, a second semiconductor material and a third semiconductor material, the second semiconductor material being between the first semiconductor material and the third semiconductor material, and the second semiconductor material comprising a slower <111> growth rate than the first semiconductor material and the third semiconductor material. 
     
     
         14 . The structure of  claim 13 , wherein the second semiconductor material comprises SiGe. 
     
     
         15 . The structure of  claim 13 , wherein a height of the faceted, raised source/drain regions is confined by the second semiconductor material. 
     
     
         16 . The structure of  claim 13 , wherein the second semiconductor material comprises a slower silicide diffusion rate than the third semiconductor material. 
     
     
         17 . The structure of  claim 16 , wherein the silicided region of the faceted, raised source/drain regions comprises a concave profile such that the silicide region in a middle of the profile is farther away from an underlying substrate than at edges of the profile. 
     
     
         18 . The structure of  claim 12 , wherein the stack of epitaxial semiconductor material comprises a first semiconductor material and a second semiconductor material which comprises a slower growth rate than the first semiconductor material in a <111> plane. 
     
     
         19 . The structure of  claim 12 , wherein an upper semiconductor material of the stack of epitaxial semiconductor material are remote from sidewalls of the gate structure. 
     
     
         20 . A method comprising:
 forming a gate structure on a substrate; and   forming faceted, raised source/drain regions adjacent to the gate structure and comprising at least two different semiconductor materials.