Inventor · disambiguated record
Matthew W. Stoker
Also filed as: STOKER MATTHEW · STOKER MATTHEW W · STOKER MATTHEW WAHLQUIST
23 granted patents·6 pending applications·186 citations·filing 2003–2021
95Inventor score
Top patents by PatentIndex Score
29 records- 0196US7238580B2Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentrationFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jul 3, 2007·59 cites·16 claims
- 0294US8492234B2Field effect transistor deviceCHAN KEVIN K·Filed 2010·Granted Jul 23, 2013·16 cites·12 claims
- 0393US10396078B2Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 27, 2019·9 cites·16 claims
- 0493US10020307B1Integrated circuit structure including laterally recessed source/drain epitaxial region and method of forming sameGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 10, 2018·9 cites·11 claims
- 0592US8361859B2Stressed transistor with improved metastabilityIBM·Filed 2010·Granted Jan 29, 2013·13 cites·15 claims
- 0689US7932189B2Process of forming an electronic device including a layer of discontinuous storage elementsFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 26, 2011·16 cites·20 claims
- 0787US8940595B2Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levelsIBM·Filed 2013·Granted Jan 27, 2015·8 cites·20 claims
- 0886US9190406B2Fin field effect transistors having heteroepitaxial channelsIBM·Filed 2014·Granted Nov 17, 2015·7 cites·20 claims
- 0986US7029980B2Method of manufacturing SOI template layerFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Apr 18, 2006·25 cites·17 claims
- 1083US10204984B1Methods, apparatus and system for forming increased surface regions within EPI structures for improved trench silicideGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 12, 2019·3 cites·20 claims
- 1183US9287399B2Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levelsIBM·Filed 2014·Granted Mar 15, 2016·5 cites·16 claims
- 1278US8618617B2Field effect transistor deviceIBM·Filed 2013·Granted Dec 31, 2013·3 cites·9 claims
- 1375US7700438B2MOS device with nano-crystal gate structureFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 20, 2010·5 cites·15 claims
- 1472US9236477B2Graphene transistor with a sublithographic channel widthGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 12, 2016·2 cites·20 claims
- 1571US9673295B2Contact resistance optimization via EPI growth engineeringGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 6, 2017·3 cites·20 claims
- 1667US7928502B2Transistor devices with nano-crystal gate structuresFREESCALE SEMICONDUCTOR INC·Filed 2010·Granted Apr 19, 2011·2 cites·19 claims
- 1757US8426265B2Method for growing strain-inducing materials in CMOS circuits in a gate first flowBAI BO·Filed 2010·Granted Apr 23, 2013·1 cites·16 claims
- 1852US7683443B2MOS devices with multi-layer gate stackFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Mar 23, 2010·0 cites·16 claims
- 1950US8779525B2Method for growing strain-inducing materials in CMOS circuits in a gate first flowIBM·Filed 2013·Granted Jul 15, 2014·0 cites·19 claims
- 2049US10121706B2Semiconductor structure including two-dimensional and three-dimensional bonding materialsGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 6, 2018·0 cites·9 claims
- 2149US2023146952A1Transistor with faceted, raised source/drain regionGLOBALFOUNDRIES US INC·Filed 2021·Application pending·0 cites
- 2248US10910471B2Device with large EPI in FinFETs and method of manufacturingGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 2, 2021·0 cites·10 claims
- 2348US2013134444A1Stressed transistor with improved metastabilityIBM·Filed 2013·Application pending·0 cites
- 2447US10529831B1Methods, apparatus, and system for forming epitaxial formations with reduced risk of mergingGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 7, 2020·0 cites·12 claims
- 2542US2015097270A1Finfet with relaxed silicon-germanium finsIBM·Filed 2013·Application pending·0 cites
- 2639US7510956B2MOS device with multi-layer gate stackFRESSSCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 31, 2009·0 cites·22 claims
- 2738US2018197734A1Buffer layer to inhibit wormholes in semiconductor fabricationGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2838US2007096226A1MOSFET dielectric including a diffusion barrierLIU CHUN-LI·Filed 2005·Application pending·0 cites
- 2930US2006189079A1Method of forming nanoclustersMERCHANT TUSHAR P·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →