US2013134444A1PendingUtilityA1
Stressed transistor with improved metastability
Est. expiryNov 9, 2030(~4.3 yrs left)· nominal 20-yr term from priority
Inventors:Thomas N. AdamStephen W. BedellAbhishek DubeEric C. HarleyJudson R. HoltAlexander ReznicekDevendra K. SadanaDominic J. SchepisMatthew W. StokerKeith H. Tabakman
H10D 64/0113H10W 20/083H10W 20/056H10W 20/0696H10D 62/021H10D 30/0275H10D 84/0186H10D 84/0167H10D 84/038H10D 84/017H10D 30/797H10D 30/60H01L 29/78
48
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Claims
Abstract
An embedded, strained epitaxial semiconductor material, i.e., an embedded stressor element, is formed at the footprint of at least one pre-fabricated field effect transistor that includes at least a patterned gate stack, a source region and a drain region. As a result, the metastability of the embedded, strained epitaxial semiconductor material is preserved and implant and anneal based relaxation mechanisms are avoided since the implants and anneals are performed prior to forming the embedded, strained epitaxial semiconductor material.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor structure comprising:
at least one field effect transistor located within an active device region of a semiconductor substrate, said at least one field effect transistor comprising a patterned gate stack, a source region and a drain region, wherein at least a portion of said source region and a portion of said drain region include a metastable strained epitaxial semiconductor material disposed therein; a dielectric material located on exposed surfaces of the semiconductor substrate and surrounding the at least one field effect transistor, said dielectric material having contact openings that expose an upper surface of said metastable strained epitaxial semiconductor material; and a conductive contact material located within said contact openings and directly on an upper surface of said metastable strained epitaxial semiconductor material.
2 . The semiconductor structure of claim 1 wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe.
3 . The semiconductor structure of claim 2 wherein said SiGe contains a Ge content of from 15 atomic % to 60 atomic %.
4 . The semiconductor structure of claim 1 wherein said at least one field effect transistor is a pFET and said strained epitaxial semiconductor material consists essentially of SiGe:C.
5 . The semiconductor structure of claim 4 wherein said SiGe:C contains a C content from 0.5 atomic % to 3.0 atomic %.
6 . The semiconductor structure of claim 1 wherein said at least one field effect transistor is an nFET and said second strained epitaxial semiconductor material consists essentially of Si:C.
7 . The semiconductor structure of claim 6 wherein said Si:C contains a C content from 0.5 atomic % to 3.0 atomic %.
8 . The semiconductor structure of claim 1 wherein a portion of said metastable strained semiconductor material extends above a planar upper surface of said semiconductor substrate.
9 . The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material has a same crystallographic orientation as that of the semiconductor substrate.
10 . The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material imparts a strain to a channel region which is located in the semiconductor substrate, beneath the patterned gate stack and between the source region and the drain region.
11 . The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is spaced apart from a spacer that is located on vertical sidewalls of the patterned gate stack.
12 . The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is located within a trench having vertical sidewalls, and said vertical sidewalls of said trench are in contact with a different semiconductor material within the source region and drain region.
13 . The semiconductor structure of claim 1 wherein said at least one field effect transistor comprises an nFET within an nFET device region and a PFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within only one of nFET region or pFET region.
14 . The semiconductor structure of claim 1 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within both said nFET region and said pFET region.
15 . The semiconductor structure of claim 1 wherein said metastable strained epitaxial semiconductor material is located within the entirety of said source region and said drain region.
16 . The semiconductor structure of claim 15 wherein said metastable strained epitaxial semiconductor material has a sidewall edge that is aligned with and located beneath a vertical edge of said patterned gate stack.
17 . The semiconductor structure of claim 16 wherein said metastable strained epitaxial semiconductor material has a portion that extends above a planar upper surface of said semiconductor substrate.
18 . The semiconductor structure of claim 16 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within only one of nFET region or pFET region.
19 . The semiconductor structure of claim 16 wherein said at least one field effect transistor comprises an nFET within an nFET device region and aPFET within a pFET device region, and wherein said metastable strained epitaxial semiconductor material is located within both said nFET region and said pFET region.
20 . The semiconductor structure of claim 19 wherein said metastable strained epitaxial semiconductor material within the nFET device region is different from said metastable strained epitaxial semiconductor material within said pFET device region.Cited by (0)
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