Memory devices supporting read/modify/write memory operations involving both volatile memory and nonvolatile memory

Abstract

Exemplary apparatus includes a nonvolatile memory, a volatile memory separate from the nonvolatile memory, and a controller configured to access the volatile memory and the nonvolatile memory. Exemplary volatile memory is configured to function as a read/write cache. The controller may be configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory. Exemplary devices may have a host interface and may include a data connection configured to perform double data rate data transfer. Exemplary volatile memory may support byte-granularity memory read operations, and the density of the volatile memory may be substantially less than the density of the nonvolatile memory.

What is claimed is: 
     
         1 . An apparatus comprising:
 a nonvolatile memory;   a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a read/write cache; and   a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory,   wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer;   wherein the volatile memory supports byte-granularity memory read operations; and   wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory.   
     
     
         2 . A device comprising:
 a nonvolatile memory;   a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a cache; and   a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory.   
     
     
         3 . The device of  claim 2 , wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer. 
     
     
         4 . The device of  claim 2 , wherein the volatile memory supports byte-granularity memory read operations. 
     
     
         5 . The device of  claim 2 , further comprising an address decoder and an energy storage device. 
     
     
         6 . The device of  claim 5 , wherein the address decoder is distinct from the controller. 
     
     
         7 . The device of  claim 2 , wherein the cache is used as a static random access memory for more than one page of memory of the nonvolatile memory. 
     
     
         8 . The device of  claim 2 , wherein the controller includes an address generator. 
     
     
         9 . The device of  claim 2 , wherein the controller includes read/write combination control logic. 
     
     
         10 . The device of  claim 2 , wherein the controller includes an audio interface. 
     
     
         11 . The device of  claim 2 , wherein the controller includes a video interface. 
     
     
         12 . The device of  claim 2 , wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory. 
     
     
         13 . The device of  claim 2 , wherein the density of the volatile memory is less than 10% of the density of the nonvolatile memory. 
     
     
         14 . The device of  claim 2 , wherein the volatile memory includes a register that is used in connection with the read/modify/write memory operation. 
     
     
         15 . The device of  claim 2 , wherein the nonvolatile memory operates in parallel with and concurrently with respect to the volatile memory. 
     
     
         16 . An apparatus comprising:
 a nonvolatile memory;   a volatile memory separate from the nonvolatile memory, wherein the volatile memory is configured to function as a read/write cache; and   a controller configured to access the volatile memory and the nonvolatile memory, the controller configured to perform a read/modify/write memory operation that involves both the volatile memory and the nonvolatile memory,   wherein the device has a host interface and the device further comprises a data connection configured to perform double data rate data transfer;   wherein the volatile memory supports byte-granularity memory read operations;   wherein the density of the volatile memory is substantially less than the density of the nonvolatile memory; and   wherein the nonvolatile memory is configured to operate in parallel with and concurrently with respect to the volatile memory.   
     
     
         17 . The device of  claim 16 , wherein the cache is used as a static random access memory for more than one page of memory of the nonvolatile memory. 
     
     
         18 . The device of  claim 16 , wherein the controller includes read/write combination control logic. 
     
     
         19 . The device of  claim 16 , wherein the density of the volatile memory is less than 10% of the density of the nonvolatile memory. 
     
     
         20 . The device of  claim 16 , wherein the controller is configured to perform a read page as volatile memory command and to perform a write page as volatile memory command. 
     
     
         21 . The device of  claim 16 , wherein the controller is configured to perform a read byte level command and to perform a write byte level command. 
     
     
         22 . The device of  claim 16 , wherein the controller is configured to perform a command to read a page in the volatile memory of a particular block of the nonvolatile memory. 
     
     
         23 . The device of  claim 16 , wherein the controller is configured to perform load/store operations with respect to the volatile memory and an assigned block of the nonvolatile memory.