Communication channel calibration for drift conditions

Abstract

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

1 . (canceled) 
     
     
         2 . A controller to control a memory component, the controller comprising:
 interface circuitry to receive information from the memory component, via at least one link, wherein the interface circuitry is to sample the information from the memory component according to edges of a clock signal; and   phase adjustment circuitry to vary a phase of the edges of the clock signal;   wherein the phase adjustment circuitry is to establish an operating value of the phase during a calibration operation, the operating value to be applied to the sampling of the information, and wherein the phase adjustment circuitry is to from-time-to-time adjust the operating value in response to drift between the operating value and a timing point for the sampling of the information by the controller, the drift being detected subsequent to establishment of the operating value.   
     
     
         3 . The controller of  claim 2  wherein:
 the memory component is to provide a predetermined data pattern to the controller, in connection with the calibration operation; and 
 during the calibration operation,
 the interface circuitry is to sample the predetermined data pattern from the memory component, according to respective phases of the clock signal, and 
 the phase adjustment circuitry is to establish the operating value, dependent on one or more of the respective phases of the clock signal, where the one or more respective phases of the clock signal each correspond to correct receipt of the predetermined data pattern. 
 
 
     
     
         4 . The controller of  claim 2  wherein:
 said controller further comprises circuitry which is to receive a predetermined data pattern from the memory component, in connection with the calibration operation; 
 during the calibration operation, the interface circuitry is to receive the predetermined data pattern from the memory component multiple times, each of the multiple times such that sampling is performed according to a respective phase of the clock signal; and 
 the phase adjustment circuitry is to establish the operating value according to a phase of the clock signal that corresponds to correct sampling of the predetermined data pattern by the controller. 
 
     
     
         5 . The controller of  claim 4  wherein:
 the clock signal is a first clock signal and the information to be received from the memory device is first information; 
 the interface circuitry also comprises a transmitter, wherein the transmitter is to transmit second information to the memory component, according to edges of a second clock signal; 
 the phase adjustment circuitry is also to vary a phase of the edges of the second clock signal; and 
 the phase adjustment circuitry is to establish an operating value of the phase of the edges of the second clock signal, during a calibration operation, the operating value of the phase of the edges of the second clock signal to be applied to the transmission by the transmitter of the second information, and wherein the phase adjustment circuitry is to from-time-to-time adjust the operating value of the phase of the edges of the second clock signal, in response to drift between the operating value of the phase of the edges of the second clock signal and a timing point for transmission of the second information. 
 
     
     
         6 . The controller of  claim 5  wherein the at least one link comprises a bidirectional link and wherein the transmission of information to the memory component and the receipt of information from the memory component each occur over the bidirectional link. 
     
     
         7 . The controller of  claim 2  wherein, during the calibration operation:
 the controller is to receive a first calibration pattern from the memory component; 
 the controller is to compare a stored data pattern with the first calibration pattern received from the memory component, as-sampled by the interface circuitry; and 
 the phase adjustment circuitry is to establish the operating value of the phase of the edges of the clock signal responsive to the comparison between the stored calibration and the first calibration pattern received from the memory component, as-sampled by the interface circuitry. 
 
     
     
         8 . The controller of  claim 7  wherein the first calibration pattern and the stored data pattern are selected by the controller. 
     
     
         9 . The controller of  claim 7  wherein the interface circuitry comprises a transmitter, and wherein the first calibration pattern is to be first transmitted by the transmitter to the memory component, and then retransmitted from the memory component back to the controller, in connection with the calibration operation. 
     
     
         10 . The controller of  claim 2  wherein, as part of the calibration operation used to establish the operating value of the phase of the edges of the clock signal, the phase adjustment circuitry is to identify timing of two data eye edges associated with correct sampling by the interface circuitry of the information from the memory component and is to establish the operating value of the phase of the edges of the clock signal dependent on a midpoint between the timing of the two data eye edges. 
     
     
         11 . The controller of  claim 10  wherein the phase adjustment circuitry, in adjusting the operating value of the phase of the edges of the clock signal in response to drift, is to, from time-to-time:
 identify a new value for timing for at least one of the two data eye edges; and 
 perform the adjusting of the operating value of the phase of the edges of the clock signal, in dependence on the new value. 
 
     
     
         12 . The controller of  claim 2  wherein the interface circuitry further comprises serialization circuitry, wherein the at least one link comprises a serial transmission line, and wherein the controller is to, during each calibration operation, receive serial data from the memory component via the serial transmission line. 
     
     
         13 . A method of controlling a memory component, using a controller, the method comprising:
 with interface circuitry of the controller, receiving information from the memory component, via at least one link, wherein receiving the information comprises sampling the information from the memory component according to edges of a clock signal; and   with phase adjustment circuitry of the controller, varying a phase of the edges of the clock signal;   wherein varying the phase comprises establishing an operating value of the phase during a calibration operation, applying the operating value to the sampling of the information and, from-time-to-time, adjusting the operating value in response to drift between the operating value and a timing point for the sampling of the information by the controller, the drift being detected subsequent to establishment of the operating value.   
     
     
         14 . The method of  claim 13  wherein:
 the memory component is to provide a predetermined data pattern to the controller, in connection with the calibration operation; and 
 the method further comprises, during the calibration operation,
 sampling the predetermined data pattern from the memory component, according to respective phases of the clock signal, and 
 establishing the operating value, dependent on one or more of the respective phases of the clock signal, where the one or more respective phases of the clock signal each correspond to correct receipt of the predetermined data pattern. 
 
 
     
     
         15 . The method of  claim 13  wherein:
 the controller is to receive a predetermined data pattern from the memory component in connection with the calibration operation; and 
 the method further comprises,
 during the calibration operation, receiving the predetermined data pattern from the memory component multiple times, each of the multiple times such that sampling is performed according to a respective phase of the clock signal, and 
 establishing the operating value according to a phase of the clock signal that corresponds to correct sampling of the predetermined data pattern by the controller. 
 
 
     
     
         16 . The method of  claim 15  wherein:
 the clock signal is a first clock signal and the information to be received from the memory device is first information; 
 the interface circuitry further comprises a transmitter; and 
 the method further comprises
 with the transmitter, transmitting second information to the memory component, according to edges of a second clock signal, 
 with the phase adjustment circuitry, also varying a phase of the edges of the second clock signal, and 
 with the phase adjustment circuitry, establishing an operating value of the phase of the edges of the second clock signal, during a calibration operation, applying the operating value of the phase of the edges of the second clock signal to the transmission by the transmitter of the second information, and, with the phase adjustment circuitry, from-time-to-time adjusting the operating value of the phase of the edges of the second clock signal, in response to drift between the operating value of the phase of the edges of the second clock signal and a timing point for transmission of the second information. 
 
 
     
     
         17 . The method of  claim 13  wherein the method further comprises, during the calibration operation:
 with the controller, comparing a stored data pattern with a first calibration pattern received from the memory component, as-sampled by the interface circuitry; and 
 with the phase adjustment circuitry, establishing the operating value of the phase of the edges of the clock signal responsive to the comparison between the stored data pattern and the first calibration pattern received from the memory component, as-sampled by the interface circuitry. 
 
     
     
         18 . The method of  claim 17  wherein the interface circuitry comprises a transmitter, wherein the method further comprises transmitting, with the memory component, the predetermined data pattern to the memory component, and wherein the predetermined data pattern is to then be retransmitted from the memory component back to the controller, in connection with the calibration operation. 
     
     
         19 . The method of  claim 13  wherein the method further comprises, as part of the calibration operation used to establish the operating value of the phase of the edges of the clock signal, and with the phase adjustment circuitry:
 identifying timing of two data eye edges associated with correct sampling by the interface circuitry of the information from the memory component; and 
 establishing the operating value of the phase of the edges of the clock signal, dependent on a midpoint between the timing of the two data eye edges. 
 
     
     
         20 . The method of  claim 19  wherein the method further comprises, with the phase adjustment circuitry, and from time-to-time:
 identifying a new value associated with the timing of at least one of the two data eye edges; and 
 performing the adjusting of the operating value of the phase of the edges of the clock signal, in dependence on the new value. 
 
     
     
         21 . A controller comprising:
 means for receiving information from a memory component, via at least one link, wherein the means for receiving is to sample the information from the memory component according to edges of a clock signal; and   means for varying a phase of the edges of the clock signal;   wherein means for varying is to establish an operating value of the phase during a calibration operation, is to apply the operating value to the sampling of the information and, from-time-to-time, is to adjust the operating value in response to drift between the operating value and a timing point for the sampling of the information by the controller, the drift being detected subsequent to establishment of the operating value.