US2023236517A1PendingUtilityA1

Method to achieve tilted patterning with a through resist thickness using projection optics

Assignee: INTEL CORPPriority: Dec 19, 2019Filed: Apr 3, 2023Published: Jul 27, 2023
Est. expiryDec 19, 2039(~13.4 yrs left)· nominal 20-yr term from priority
G03F 7/70733B81B 1/00B81C 1/00111G03F 7/201B81B 2203/0361B81C 2201/0159G03F 7/70275G03F 7/70225G03F 7/70241G03F 7/70258G02B 13/22
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Claims

Abstract

Embodiments disclosed herein include lithographic patterning systems for non-orthogonal patterning and devices formed with such patterning. In an embodiment, a lithographic patterning system comprises an actinic radiation source, where the actinic radiation source is configured to propagate light along an optical axis. In an embodiment, the lithographic patterning system further comprises a mask mount, where the mask mount is configurable to orient a surface of a mask at a first angle with respect to the optical axis. In an embodiment, the lithographic patterning system further comprises a lens module, and a substrate mount, where the substrate mount is configurable to orient a surface of a substrate at a second angle with respect to the optical axis.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An electronic device, comprising:
 a substrate; and   a plurality of pins extending out from the substrate, wherein the plurality of pins are oriented at a non-orthogonal angle with respect to the substrate.   
     
     
         2 . The electronic device of  claim 1 , wherein each pin has an aspect ratio of length to width of at least 15:1. 
     
     
         3 . The electronic device of  claim 2 , wherein the aspect ratio is at least 30:1. 
     
     
         4 . The electronic device of  claim 1 , wherein a length of each pin is approximately 250 μm or greater. 
     
     
         5 . The electronic device of  claim 1 , wherein a width of each pin is substantially uniform along a length of the pin. 
     
     
         6 . The electronic device of  claim 1 , wherein a width of each pin is non-uniform along a length of the pin. 
     
     
         7 . The electronic device of  claim 6 , wherein a first width of the pin proximate to the substrate is greater than a second width of the pin distal from the substrate. 
     
     
         8 . The electronic device of  claim 6 , wherein the plurality of pins comprises over one hundred pins. 
     
     
         9 . The electronic device of  claim 1 , wherein the plurality of pins comprises over one hundred pins. 
     
     
         10 . The electronic device of  claim 1 , wherein the non-orthogonal angle is between 0° and 45°. 
     
     
         11 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a substrate; and 
 a plurality of pins extending out from the substrate, wherein the plurality of pins are oriented at a non-orthogonal angle with respect to the substrate. 
   
     
     
         12 . The computing device of  claim 11 , wherein each pin has an aspect ratio of length to width of at least 15:1. 
     
     
         13 . The computing device of  claim 11 , wherein the plurality of pins comprises over one hundred pins. 
     
     
         14 . The computing device of  claim 11 , further comprising:
 a memory coupled to the board.   
     
     
         15 . The computing device of  claim 11 , further comprising:
 a communication chip coupled to the board.   
     
     
         16 . The computing device of  claim 11 , further comprising:
 a battery coupled to the board.   
     
     
         17 . The computing device of  claim 11 , further comprising:
 a camera coupled to the board.   
     
     
         18 . The computing device of  claim 11 , further comprising:
 a display coupled to the board.   
     
     
         19 . The computing device of  claim 11 , wherein the component is a packaged integrated circuit die. 
     
     
         20 . The computing device of  claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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