Cavity in metal interconnect structure

Abstract

An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

What is claimed is: 
     
         1 . An integrated circuit device, comprising:
 a metal interconnect over a substrate; and   a cavity within the metal interconnect;   wherein a first dielectric layer provides a roof for the cavity;   a second dielectric layer provides a floor for the cavity; and   an oxide semiconductor provides a side edge for the cavity.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the oxide semiconductor is a liner for a metal line or a metal via. 
     
     
         3 . The integrated circuit device of  claim 1 , wherein the cavity has a height that is greater than a thickness of the first dielectric layer. 
     
     
         4 . The integrated circuit device of  claim 1 , wherein the oxide semiconductor extends from the first dielectric layer to the second dielectric layer. 
     
     
         5 . An integrated circuit device, comprising:
 a metal interconnect over a substrate;   a transistor within the metal interconnect;   a dielectric structure within the metal interconnect;   a cavity within the dielectric structure;   wherein the cavity has a ceiling and a floor;   a first dielectric layer provides the ceiling;   a second dielectric layer provides the floor; and   a layer of material that provides a gate dielectric for the transistor is directly over the first dielectric layer.   
     
     
         6 . The integrated circuit device of  claim 5 , wherein the first dielectric layer has an upper surface coplanar with an upper surface of a metal structure of the metal interconnect. 
     
     
         7 . The integrated circuit device of  claim 5 , wherein the cavity has an area within which a shape of the ceiling conforms to a shape of the floor. 
     
     
         8 . The integrated circuit device of  claim 5 , wherein the cavity has an oxide ceiling, an oxide floor, and a nitride side edge. 
     
     
         9 . The integrated circuit device of  claim 5 , wherein the dielectric structure further comprises a second cavity directly below the cavity. 
     
     
         10 . The integrated circuit device of  claim 5 , further comprising:
 an array of memory cells within the metal interconnect;   wherein the cavity is between two conductive lines; and   each of the two conductive lines provides a bit line, a word line, or a source line for the array of memory cells.   
     
     
         11 . The integrated circuit device of  claim 5 , wherein:
 the transistor is one of a plurality of transistors; and   the cavity is between two adjacent word lines that provide gate electrodes for the transistors.   
     
     
         12 . The integrated circuit device of  claim 5 , wherein the layer of material comprises a high-κ dielectric. 
     
     
         13 . An integrated circuit device, comprising:
 a metal interconnect comprising a metallization layer over a substrate;   a first metal line and a second metal line within the metallization layer, wherein a top height corresponds to a top of the first metal line and the second metal line, and a bottom height corresponds to a bottom of the first metal line and the second metal line; and   a cavity between the first metal line and the second metal line, wherein a first dielectric layer provides a ceiling for the cavity and a second dielectric layer provides a floor for the cavity, the floor is above the bottom height and the ceiling is below the top height, and the floor and the ceiling are flat.   
     
     
         14 . The integrated circuit device of  claim 13 , wherein the first metal line and the second metal line provide gate electrodes for transistor. 
     
     
         15 . The integrated circuit device of  claim 14 , wherein the transistors are access control devices for memory cells. 
     
     
         16 . The integrated circuit device of  claim 13 , wherein an oxide semiconductor provides a sidewall for the cavity. 
     
     
         17 . The integrated circuit device of  claim 13 , the first metal line and the second metal line have liner that comprise an oxide semiconductor. 
     
     
         18 . The integrated circuit device of  claim 13 , wherein the cavity reduces a capacitance of a back-end-of-line transistor. 
     
     
         19 . The integrated circuit device of  claim 13 , wherein a third dielectric provides a sidewall for the cavity. 
     
     
         20 . The integrated circuit device of  claim 19 , wherein the third dielectric has a composition that is distinct from the first dielectric layer and from the second dielectric layer.