Computing System with Hardware and Methods for Handling Immediate Operands in Machine Instructions

Abstract

This disclosure relates to methods and mechanisms for matrix computing which include machine embodiments with one or more matrix storage spaces for holding matrices and arrays for computing, where a matrix or an array is accessible by its columns, by its rows, or both, individually, or concurrently. A set of methods and mechanisms to build a large capacity instruction set with multi-length instructions to load, store, and compute with these matrices and arrays are also disclosed. Methods and access control mechanisms with keys to secure, share, lock and unlock regions in the storage space for matrices and arrays under the control of an operating system or a virtual machine hypervisor by permitted threads and processes are also disclosed. Methods and mechanisms to handle long immediate operands for use by shorter instructions using a payload instruction are also disclosed. The structure of the instructions with key instruction fields and a method for determining instruction length are also disclosed.

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         14 . A computing machine comprising:
 a first instruction comprising at least one first opcode and a first immediate operand;   a subsequent instruction comprising at least one second opcode and a second immediate operand; and   a first resultant immediate operand generated by combining the first immediate operand with the second immediate operand, and   wherein, the subsequent instruction is configured to execute upon the first resultant immediate operand.   
     
     
         15 . The computing machine of  claim 14 , where in the first immediate operand is combined with the second immediate operand using a concatenation operation. 
     
     
         16 . The computing machine of  claim 14 , wherein the subsequent instruction is decoded independent of the first instruction. 
     
     
         17 . The computing machine of  claim 14 , wherein the first resultant immediate operand is used in an arithmetic operation or logical operation or a vector operation or a matrix operation. 
     
     
         18 . The computer machine of  claim 14 , wherein the first resultant immediate operand is combined with a third immediate operand of a third instruction to create a second resultant immediate operand, and wherein the second resultant immediate operand is used in a computation. 
     
     
         19 . The computing machine of  claim 14 , wherein the first instruction is a payload immediate instruction. 
     
     
         20 . A computing machine comprising:
 at least one instruction decoder that decodes a first instruction comprising at least one first opcode and a first immediate operand, wherein the first instruction is an immediate operand instruction of the computing machine; and   further, the at least one instruction decoder decodes a subsequent instruction comprising at least one second opcode and a second immediate operand, and wherein the at least one instruction decoder configures the subsequent instruction comprising the at least one second opcode to operate upon a combination of the first immediate operand and the second immediate operand.   
     
     
         21 . The computing machine of  claim 20  further comprising:
 at least one payload mechanism which comprises:
 a shifter that receives the second immediate operand at a first input; 
 a shift controller that presents a shift control value at a second input to the shifter, wherein the shifter generates a shifted value from the second immediate operand in response to the shift control value; 
 a logic circuit that combines the first immediate operand and the shifted value to generate a resultant immediate operand; and 
 an immediate operand register that stores the resultant immediate operand. 
 
 
     
     
         22 . The computing machine of  claim 21 , wherein the shift controller generates the shift control value in response to a shift value received from the instruction decoder. 
     
     
         23 . The computing machine of  claim 21 , wherein the first immediate operand is stored in the immediate operand register. 
     
     
         24 . The computing machine of  claim 21 , wherein the subsequent instruction is configured to operate upon the resultant immediate operand by the instruction decoder. 
     
     
         25 . The computing machine of  claim 21 , wherein the first instruction is a payload instruction; and wherein the first instruction is a 16-bit payload instruction or wherein the first instruction is a 32-bit payload instruction or wherein the first instruction is a 48-bit payload instruction or wherein the first instruction is a 64-bit payload instruction. 
     
     
         26 . The computing machine of  claim 21 , wherein the instruction decoder decodes the subsequent instruction of a length that is a multiple of 16 bits, and wherein the subsequent instruction comprises a plurality of 4-bit fields and/or 8-bit fields. 
     
     
         27 . A computing machine comprising:
 a first instruction comprising at least one first opcode and a first immediate operand, wherein the first instruction is a payload immediate instruction; and   a second instruction comprising at least one second opcode wherein the second instruction is configured with the at least one second opcode to operate upon the first immediate operand.   
     
     
         28 . The computing machine of  claim 27 , wherein the payload instruction is a 16-bit instruction with an immediate operand of fewer than 13-bits. 
     
     
         29 . The computing machine of  claim 27 , wherein the first instruction succeeds the second instruction. 
     
     
         30 . A method for instruction decoding comprising:
 decoding a length field (LEN) of an instruction to determine a length of the instruction; decoding an architecture field of the instruction to determine at least one subset of an instruction set architecture comprising the instruction;   decoding a co-processor field (CoP) of the instruction to determine a co-processor that operates upon the instruction; or   decoding an opcode of the instruction to concatenate the instruction with a next adjacent instruction to decode as a long instruction.   
     
     
         31 . The method of  claim 30 , wherein a LEN field in the instruction is used by a decoder to decode the instruction as a 16-bit instruction or wherein the LEN field in the instruction is used by the decoder to decode the instruction as a 32-bit instruction. 
     
     
         32 . The method of  claim 30 , wherein an instruction set architecture (ISA) field of the instruction is decoded by an instruction decoder to determine an instruction subset to configure when the instruction set architecture is partitioned into two or more instruction sub-sets. 
     
     
         33 . The method of  claim 30 , wherein a 4 bit field of the instruction comprises a LEN field, wherein the LEN field configures the length of the instruction as either 16 bits or more than 16 bits. 
     
     
         34 . The method of  claim 30 , wherein a payload instruction is decoded along with a second 16-bit instruction that receives an immediate operand or wherein the payload instruction is decoded along with a second 32-bit instruction that receives an immediate operand. 
     
     
         35 . The method of  claim 34 , wherein the payload instruction is a 16-bit instruction with an immediate operand of fewer than 13-bits. 
     
     
         36 . The method of  claim 34 , wherein the payload instruction is a 32-bit instruction with an immediate operand of fewer than 29-bits. 
     
     
         37 . The method of  claim 34 , wherein the payload instruction is a 64-bit instruction with an immediate operand of fewer than 61-bits. 
     
     
         38 . The method of  claim 30 , wherein an instruction decoder is configured to decode the co-processor field of the instruction to configure the instruction to run on a co-processor.