Computing Machine Using a Matrix Space And Matrix Pointer Registers For Matrix and Array Processing

Abstract

This disclosure relates to methods and mechanisms for matrix computing which include machine embodiments with one or more matrix storage spaces for holding matrices and arrays for computing, where a matrix or an array is accessible by its columns, by its rows, or both, individually, or concurrently. A set of methods and mechanisms to build a large capacity instruction set with multi-length instructions to load, store, and compute with these matrices and arrays are also disclosed. Methods and access control mechanisms with keys to secure, share, lock and unlock regions in the storage space for matrices and arrays under the control of an operating system or a virtual machine hypervisor by permitted threads and processes are also disclosed. Methods and mechanisms to handle long immediate operands for use by shorter instructions using a payload instruction are also disclosed. The structure of the instructions with key instruction fields and a method for determining instruction length are also disclosed.

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         14 . A computing system comprising:
 a matrix space to store at least one array, the matrix space separate from system memory, the matrix space controlled by a control logic circuit to configure and control matrix operations,   wherein the control logic circuit is separate from a system memory controller,   wherein the matrix space is configured to be accessible by rows and by columns,   wherein two or more elements of a row of the at least one array are accessible simultaneously at a row port in response to a row address,   and wherein two or more elements of a column of the at least one array are accessible simultaneously at a column port in response to a separate column address.   
     
     
         15 . The computing system of  claim 14 , wherein an individual element included in the matrix space is concurrently accessible by the row containing the individual element and by the column containing the individual element. 
     
     
         16 . The computing system of  claim 14 , wherein one or more elements of the row of the at least one array accessible at the row port are concurrently accessible with one or more elements of the column of the at least one array accessible at the column port. 
     
     
         17 . The computing system of  claim 14 , wherein an origin of the at least one array comprises a row number and a column number. 
     
     
         18 . The computing system of  claim 14 , wherein size of the at least one array comprises a first number of rows in the at least one array, and a second number of columns in the at least one array. 
     
     
         19 . The computing system of  claim 14 , wherein a portion of the matrix space is pre-allocated to store the at least one array. 
     
     
         20 . The computing system of  claim 14 , further comprising at least one mechanism to control a power state or a clock associated with the matrix space. 
     
     
         21 . The computing system of  claim 14 , further comprising at least one execution unit coupled to the matrix space via at least one row port or via at least one column port, wherein the at least one execution unit is configured to use the at least one array in a computation. 
     
     
         22 . The computing system of  claim 14 , further comprising:
 one or more load matrix instructions; or   one or more store matrix instructions.   
     
     
         23 . The computing system of  claim 14 , further comprising a matrix pointer register configured to store an origin of the at least one array, a size of the at least one array, and a type of the at least one array. 
     
     
         24 . The computing system of  claim 23 , wherein the type of the at least one array identifies a type of elements in the at least one array in the matrix space, wherein the type is one of: byte, short integer, 32-bit integer, 64-bit integer, pointer to a memory location, half precision floating point number, single precision floating point number, double precision floating point number, string, ordered quad of integers, ordered quad of floating point numbers, ordered triad of integers, ordered triad of floating point numbers, ordered pair of integers, ordered pair of floating point numbers, ordered quad of bytes, ordered quad of nibbles, ordered triad of bytes, ordered triad of nibbles, ordered pair of bytes, ordered pair of nibbles, and a user defined type. 
     
     
         25 . The computing system of  claim 23 , further comprising:
 at least one matrix instruction that references the at least one array, wherein the at least one matrix instruction comprises an operand that is an index of the matrix pointer register.   
     
     
         26 . The computing system of  claim 25 , wherein the at least one matrix instruction configured to operate upon the at least one array and at least one vector that comprises one or more scalars or packed and ordered groups of values. 
     
     
         27 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to access a diagonal of the at least one array. 
     
     
         28 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to access a transpose of a portion of the at least one array, or a triangular portion of the at least one array, or a multi-diagonal portion of the at least one array. 
     
     
         29 . The computing system of  claim 25 , wherein and the at least one matrix instruction is configured to operate on complex number elements of the at least one array when the type is one of: ordered pair of bytes or ordered pair of integers or ordered pair of short integers or ordered pair of floating point numbers, wherein a complex number element is represented as an ordered pair. 
     
     
         30 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to perform a matrix multiplication operation or an array multiplication operation. 
     
     
         31 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to count elements of a row of the at least one array, reorder the elements of the row of the at least one array, or sum the elements of the row of the at least one array. 
     
     
         32 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to count elements of a column of the at least one array, reorder the elements of the column of the at least one array, or sum the elements of the column of the at least one array. 
     
     
         33 . The computing system of  claim 25 , wherein the at least one matrix instruction is configured to access the at least one array in the matrix space, securely, and wherein the at least one matrix instruction references the at least one array in response to not failing a security check. 
     
     
         34 . An array processing unit comprising a matrix space, separate from a system memory, and controlled by a control logic circuit to configure and control operations on a portion of the matrix space, wherein the matrix space is configured to be accessible by rows and by columns;
 at least one row port coupled to the matrix space that is configured to access a portion of a row of the matrix space, wherein elements of the portion of the row are accessed simultaneously at the at least one row port in response to a row address;   at least one column port coupled to the matrix space that is configured to access a portion of a column of the matrix space, wherein elements of the portion of the column are accessed simultaneously at the at least one column port in response to a column address.   
     
     
         35 . The array processing unit of  claim 34 , wherein a portion of the matrix space is accessed to read, write, set, clear, restore, transport, count, reorder, sort, scale, negate, invert, test, compare, operate on, or manipulate one or more elements in the matrix space. 
     
     
         36 . The array processing unit of  claim 34 , wherein the at least one row port and the at least one column port are oriented perpendicular to one another in two dimensions. 
     
     
         37 . The array processing unit of  claim 34 , further comprising a matrix pointer register configured to store an origin of an allocation in the matrix space, a size of the allocation, and a type. 
     
     
         38 . The array processing unit of  claim 37 , wherein contents of the matrix pointer register determine an allocation of space in the matrix space. 
     
     
         39 . The array processing unit of  claim 37 , wherein the allocation is associated with a sub-matrix, a portion of an array, multi-diagonal portions of a matrix, matroids, or a zero matrix, 
     
     
         40 . The array processing unit of  claim 37 , further comprising at least one matrix instruction that references the allocation, wherein the at least one matrix instruction comprises an operand that is an index of the matrix pointer register. 
     
     
         41 . The array processing unit of  claim 40 , wherein the at least one matrix instruction is configured to concurrently access the rows and the columns of at least one array. 
     
     
         42 . A method for array computing comprising:
 providing a method to store at least one array a matrix space, the matrix space separate from system memory, the matrix space controlled by a control logic circuit to configure and control matrix operations,   wherein the control logic circuit is separate from a system memory controller,   wherein the matrix space is configured to be accessible by rows and by columns,   wherein two or more elements of a row of the at least one array are accessible simultaneously at a row port in response to a row address,   and wherein two or more elements of a column of the at least one array are accessible simultaneously at a column port in response to a separate column address.   
     
     
         43 . The method of  claim 42 , further comprising a method to configure an allocation of space for the at least one array.