Three-dimensional semiconductor memory device and method of fabricating the same

Abstract

Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

1 .- 27 . (canceled) 
     
     
         28 . A semiconductor memory device, comprising:
 a substrate within one memory chip;   a plurality of memory regions on the substrate, the plurality of memory regions being arranged two-dimensionally;   a cutting structure on the substrate and surrounding each of the plurality of memory regions, the cutting structure being configured to separate the plurality of memory regions from each other, the cutting structure including a first cutting structure and a second cutting structure that extend parallel to each other and are between adjacent ones of the plurality of memory regions; and   a through contact between the first and second cutting structures.   
     
     
         29 . The device of  claim 28 , wherein each of the plurality of memory regions includes:
 a plurality of electrodes that are stacked on the substrate; and   a vertical channel structure that penetrates the plurality of electrodes and is connected to the substrate.   
     
     
         30 . The device of  claim 28 ,
 wherein the substrate includes a plurality of semiconductor layers that are disposed in the plurality of memory regions, respectively,   wherein the cutting structure is configured to separate the plurality of semiconductor layers from each other.   
     
     
         31 . The device of  claim 30 , wherein the substrate further includes a dummy semiconductor layer between the first and second cutting structures. 
     
     
         32 . The device of  claim 31 , wherein the through contact extends further downward than the dummy semiconductor layer. 
     
     
         33 . The device of  claim 28 , further comprising:
 a peripheral circuit structure below the substrate,   wherein the through contact is electrically connected to the peripheral circuit structure.   
     
     
         34 . The device of  claim 28 , further comprising:
 a through contact region between the first and second cutting structures, and   wherein the through contact is disposed in the through contact region.   
     
     
         35 . The device of  claim 34 ,
 wherein the substrate includes a dielectric pattern disposed in the through contact region, and   wherein the through contact penetrates the dielectric pattern.   
     
     
         36 . The device of  claim 28 ,
 wherein the cutting structure includes a plurality of dummy contacts and a spacer that surrounds the dummy contacts, and   wherein the dummy contacts are arranged to surround each of the plurality of memory regions.   
     
     
         37 . The device of  claim 28 , wherein the substrate further includes a metal pattern at a lower portion thereof. 
     
     
         38 . A semiconductor memory device, comprising:
 a substrate;   a plurality of memory regions on the substrate, the plurality of memory regions being arranged two-dimensionally;   a cutting structure on the substrate and surrounding each of the plurality of memory regions; and   a through contact between adjacent ones of the plurality of memory regions,   wherein the substrate includes a dummy semiconductor layer defined by the cutting structure, and   wherein the through contact is on the dummy semiconductor layer.   
     
     
         39 . The device of  claim 38 , wherein each of the plurality of memory regions includes:
 a plurality of electrodes that are stacked on the substrate; and   a vertical channel structure that penetrates the plurality of electrodes and is connected to the substrate.   
     
     
         40 . The device of  claim 38 , wherein the through contact extends further downward than the dummy semiconductor layer. 
     
     
         41 . The device of  claim 38 , further comprising:
 a peripheral circuit structure below the substrate,   wherein the through contact is electrically connected to the peripheral circuit structure.   
     
     
         42 . The device of  claim 38 , further comprising:
 a through contact region on the dummy semiconductor layer,   wherein the substrate further includes a dielectric pattern disposed in the through contact region, and   wherein the through contact is disposed in the through contact region.   
     
     
         43 . A semiconductor memory device, comprising:
 a substrate;   a first memory region and a second memory region on the substrate;   a cutting structure on the substrate and being configured to separate the first and second memory regions from each other, the cutting structure including a first cutting structure and a second cutting structure that extend parallel to each other in a first direction; and   a through contact between the first and second cutting structures.   
     
     
         44 . The device of  claim 43 , wherein the first and second cutting structures are between the first and second memory regions that are adjacent to each other in a second direction. 
     
     
         45 . The device of  claim 43 , wherein each of the first and second memory regions includes:
 a plurality of electrodes that are stacked on the substrate; and   a vertical channel structure that penetrates the plurality of electrodes and is connected to the substrate.   
     
     
         46 . The device of  claim 43 , further comprising:
 a through contact region between the first and second cutting structures,   wherein the through contact is disposed in the through contact region.   
     
     
         47 . The device of  claim 46 ,
 wherein the substrate includes a dielectric pattern disposed in the through contact region, and   wherein the through contact penetrates the dielectric pattern.