Voltage supply selection circuit and methods for operating the same

Abstract

A circuit includes a control circuit configured to receive a selection signal transitioning within a first voltage domain; and generate, based on the selection signal, a first control signal transitioning within a second voltage domain different from the first voltage domain. The circuit further includes a switch circuit operatively coupled to the control circuit and comprising a first header transistor coupled to a first voltage supply transitioning within the second voltage domain, and gated by the first control signal; and a second header transistor coupled to a second voltage supply transitioning within the first voltage domain, and gated by a second control signal that is logically inverse to the first control signal. The first header transistor and the second header transistor are complementarily turned on so as to provide an output voltage equal to either the first voltage supply or the second voltage supply.

What is claimed is: 
     
         1 . A circuit, comprising:
 a control circuit configured to:
 receive a selection signal transitioning within a first voltage domain; and 
 generate, based on the selection signal, a first control signal transitioning within a second voltage domain different from the first voltage domain; and 
   a switch circuit operatively coupled to the control circuit and comprising:
 a first header transistor coupled to a first voltage supply transitioning within the second voltage domain, and gated by the first control signal; and 
 a second header transistor coupled to a second voltage supply transitioning within the first voltage domain, and gated by a second control signal that is logically inverse to the first control signal; 
   wherein the first header transistor and the second header transistor are complementarily turned on so as to provide an output voltage equal to either the first voltage supply or the second voltage supply.   
     
     
         2 . The circuit of  claim 1 , wherein the control circuit comprises a level shifter powered by the first voltage supply, and configured to receive the selection signal and shift the selection signal from the first voltage domain to the second voltage domain. 
     
     
         3 . The circuit of  claim 2 , wherein the switch circuit comprises:
 a third header transistor coupled to the first header transistor in series, wherein the third header transistor is gated by a third control signal transitioning within the first voltage domain; and   a fourth header transistor coupled to the second header transistor in series, wherein the fourth header transistor is gated by a fourth control signal that is logically inverse to the third control signal.   
     
     
         4 . The circuit of  claim 3 , wherein the first and second control signals are generated based on the shifted selection signal. 
     
     
         5 . The circuit of  claim 3 , wherein each of the first to fourth header transistors includes a p-type metal-oxide-semiconductor (PMOS) transistor. 
     
     
         6 . The circuit of  claim 5 , wherein the second and fourth header transistors each have its V SG  equal to or less than 0 volts (V) when providing the output voltage equal to the first voltage supply, and the first and third header transistors each have its V SG  equal to or less than 0 V when providing the output voltage equal to the second voltage supply. 
     
     
         7 . The circuit of  claim 3 , further comprising:
 a first NOR-type SR latch;   one or more first delay circuits coupled to the first NOR-type SR latch;   a second NOR-type SR latch; and   one or more second delay circuits coupled to the second NOR-type SR latch;   wherein, during transition between the first voltage supply and the second voltage supply, the first to fourth header transistors are each configured to be turned on through the first NOR-type SR latch, the one or more first delay circuits, the second NOR-type SR latch, and the one or more second delay circuits.   
     
     
         8 . The circuit of  claim 3 , further comprising:
 a first NAND-type SR latch;   one or more first delay circuits coupled to the first NAND-type SR latch;   a second NAND-type SR latch; and   one or more second delay circuits coupled to the second NAND-type SR latch;   wherein, during transition between the first voltage supply and the second voltage supply, the first to fourth header transistors are each configured to be turned off through the first NAND-type SR latch, the one or more first delay circuits, the second NAND-type SR latch, and the one or more second delay circuits.   
     
     
         9 . The circuit of  claim 1 , further comprising:
 a maximum voltage selection circuit configured to select a greater one of the first voltage supply or second voltage supply;   wherein the control circuit comprises a level shifter powered by the greater one of the first voltage supply or second voltage supply, and configured to receive the selection signal and shift the selection signal from the first voltage domain to the second voltage domain.   
     
     
         10 . The circuit of  claim 9 , wherein the first and second control signals are generated based on the shifted selection signal. 
     
     
         11 . The circuit of  claim 9 , further comprising:
 a NOR-type SR latch;   one or more delay circuits coupled to the NOR-type SR latch;   wherein, during transition between the first voltage supply and the second voltage supply, the first to second header transistors are each configured to be turned on through the NOR-type SR latch and the one or more delay circuits.   
     
     
         12 . The circuit of  claim 9 , further comprising:
 a NAND-type SR latch;   one or more delay circuits coupled to the NAND-type SR latch;   wherein, during transition between the first voltage supply and the second voltage supply, the first to second header transistors are each configured to be turned off through the NAND-type SR latch and the one or more delay circuits.   
     
     
         13 . A circuit, comprising:
 a control circuit configured to:
 receive a selection signal transitioning within a first voltage domain; and 
 generate, based on the selection signal, a first control signal and a second control signal transitioning within a second voltage domain different than the first voltage domain, wherein the first control signal and the second control single are logically inverse to each other; and 
   a switch circuit operatively coupled to the control circuit and comprising:
 a first header transistor coupled to a first voltage supply transitioning within the second voltage domain, and gated by the first control signal; and 
 a second header transistor coupled to a second voltage supply transitioning within the first voltage domain, and gated by the second control signal; 
   wherein the first header transistor and the second header transistor are complementarily turned on so as to couple either the first voltage supply or the second voltage supply to an output node.   
     
     
         14 . The circuit of  claim 13 , wherein the switch circuit further comprises:
 a third header transistor coupled to the first header transistor in series, wherein the third header transistor is gated by a third control signal transitioning in the first voltage domain; and   a fourth header transistor coupled to the second header transistor in series, wherein the fourth header transistor is gated by a fourth control signal logically inverse to the third control signal.   
     
     
         15 . The circuit of  claim 14 , wherein each of the first to fourth header transistors is a p-type metal-oxide-semiconductor (PMOS) transistor, and wherein the output node is directly connected to a drain of the second header transistor and a drain of the third header transistor. 
     
     
         16 . The circuit of  claim 14 , wherein the control circuit comprises:
 an even number of first inverters configured to receive the selection signal in the first voltage domain and generate the first and second control signals;   a level shifter configured to shift the selection signal to the second voltage domain; and   an even number of second inverters configured to receive the shifted selection signal and generate the third and fourth control signals.   
     
     
         17 . The circuit of  claim 13 , wherein each of the first and second header transistors is a p-type metal-oxide-semiconductor (PMOS) transistor, and wherein the output node is directly connected to a drain of the first header transistor and a drain of the second header transistor. 
     
     
         18 . The circuit of  claim 17 , wherein the control circuit comprises:
 a level shifter configured to shift the selection signal transitioning in the first voltage domain to the second voltage domain and output the shifted selection signal as the first control signal; and   an odd number of inverters configured to invert the shifted selection signal as the second control signal.   
     
     
         19 . A method for selecting a voltage supply, comprising:
 receiving a selection signal transitioning in a first voltage domain;   generating, based on the selection signal, a first control signal and a second control signal that are logically inverse to each other and transition within a second voltage domain different from the first voltage domain;   coupling a first voltage supply to an output node through a first header transistor that is gated by the second control signal, wherein the first voltage supply transitions within the first voltage domain; and   decoupling a second voltage supply from the output node through a second header transistor that is gated by the first control signal, wherein the second voltage supply transitions within the second voltage domain.   
     
     
         20 . The method of  claim 19 , wherein each of the first and second header transistors is a p-type metal-oxide-semiconductor (PMOS) transistor, and wherein the output node is directly connected to one of: a drain of the first header transistor or a drain of the second header transistor.