Systems and methods for implementing a scalable system

Abstract

Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

What is claimed is: 
     
         1 . A multi-chip system comprising:
 a first chip;   a second chip;   an interfacing bar coupled with the first chip and the second chip, the interfacing bar including:
 an electrical-to-optical converter component; 
 an optical-to-electrical converter component; and 
 one or more waveguides extending between the electrical-to-optical converter component and the optical-to-electrical converter component. 
   
     
     
         2 . The multi-chip system of  claim 1 , further comprising a third chip coupled with the interfacing bar along a longitudinal length of the interfacing bar, wherein the second chip is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip. 
     
     
         3 . The multi-chip system of  claim 2 , wherein the interfacing bar comprises a routing layer including one or more metal wiring layers. 
     
     
         4 . The multi-chip system of  claim 3 , wherein the first chip and the third chip are electrically connected through the one or more metal wiring layers. 
     
     
         5 . The multi-chip system of  claim 1 , further comprising a routing layer between the interfacing bar and the first chip and the second chip. 
     
     
         6 . The multi-chip system of  claim 5 , wherein the first chip and the second chip are embedded in a molding compound layer. 
     
     
         7 . The multi-chip system of  claim 6 , wherein the interfacing bar is bonded to the routing layer with a plurality of solder bumps. 
     
     
         8 . The multi-chip system of  claim 6 , wherein the plurality of solder bumps is a plurality of micro bumps. 
     
     
         9 . The multi-chip system of  claim 1 , wherein the interfacing bar is embedded in 2.5D package structure. 
     
     
         10 . The multi-chip system of  claim 9 , wherein the interfacing bar is laterally adjacent a plurality of conductive pillars in the 2.5D package structure. 
     
     
         11 . The multi-chip system of  claim 10 , wherein the 2.5D package structure includes a top redistribution layer (RDL), a bottom RDL, and an insulating material between the top RDL and the bottom RDL, wherein the interfacing bar is embedded in the insulating material. 
     
     
         12 . The multi-chip system of  claim 11 , wherein the interfacing bar is bonded to the top RDL with a plurality of solder bumps. 
     
     
         13 . The multi-chip system of  claim 12 , wherein the plurality of solder bumps is a plurality of micro bumps. 
     
     
         14 . The multi-chip system of  claim 1 , wherein the interfacing bar is coupled with a first input output region along a first chip edge of the first chip, and is coupled with a second input/output region that is internal to chip edges of the second chip. 
     
     
         15 . The multi-chip system of  claim 1 , wherein the first chip is a first logic chip. 
     
     
         16 . The multi-chip system of  claim 15 , wherein the second chip is a memory chip. 
     
     
         17 . The multi-chip system of  claim 15 , wherein the second chip is a second logic chip. 
     
     
         18 . The multi-chip system of  claim 1 , wherein the first chip and the second chip are both memory chips. 
     
     
         19 . The multi-chip system of  claim 1 , further comprising:
 a third chip coupled with the interfacing bar along a longitudinal length of the interfacing bar, wherein the second chip is coupled with the interfacing bar along the longitudinal length of the interfacing bar further away from the first chip than the third chip; and   a second interfacing bar coupled with the first chip and the third chip, the second interfacing bar including a die-to-die routing electrically connecting the first chip and the third chip within one or more metal routing layers of the second interfacing bar.   
     
     
         20 . The multi-chip system of  claim 19 , wherein the interfacing bar is flexible.