Facet-free epitaxial structures for semiconductor devices

Abstract

The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a fin structure on a substrate;   a dielectric layer on a top surface of the fin structure;   an amorphous layer on the dielectric layer; and   an epitaxial layer on the amorphous layer, a sidewall surface of the dielectric layer, and a sidewall surface of the fin structure.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the epitaxial layer is facet-free and has a substantially uniform thickness on the amorphous layer and the fin structure. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the fin structure comprises a fin top portion and a fin bottom portion, and wherein a width of the fin top portion is less than a width of the fin bottom portion. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the epitaxial layer is on a top surface of the fin bottom portion. 
     
     
         5 . The semiconductor device of  claim 3 , wherein a ratio of a thickness of the epitaxial layer to the width of the fin bottom portion ranges from about 0.05 to about 0.5. 
     
     
         6 . The semiconductor device of  claim 3 , wherein a ratio of the width of the fin top portion to the width of the fin bottom portion ranges from about 0.1 to about 0.9. 
     
     
         7 . The semiconductor device of  claim 3 , wherein the fin top portion comprises a plurality of semiconductor layers, and wherein the epitaxial layer is on sidewall surfaces of the plurality of semiconductor layers. 
     
     
         8 . The semiconductor device of  claim 3 , wherein the fin top portion comprises a plurality of semiconductor layers, and wherein the epitaxial layer wraps around the plurality of semiconductor layers. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising a gate structure surrounding the fin top portion and adjacent to the epitaxial layer. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising an additional fin structure adjacent to the fin structure, wherein:
 the additional fin structure comprises a fin top portion and a fin bottom portion,   a width of the fin bottom portion is greater than a width of the fin top portion, and   the additional fin structure comprises a dopant different from the fin structure.   
     
     
         11 . The semiconductor device of  claim 1 , wherein the dielectric layer comprises silicon oxide and the amorphous layer comprises silicon. 
     
     
         12 . A semiconductor device, comprising:
 a fin structure on a substrate, wherein the fin structure comprises a fin bottom portion and a fin top portion wider than the fin bottom portion;   a dielectric layer on the fin top portion;   an amorphous layer on the dielectric layer; and   an epitaxial layer on a top surface of the amorphous layer, a top surface of the fin bottom portion, a sidewall surface of the amorphous layer, a sidewall surface of the dielectric layer, and a sidewall surface of the fin top portion.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the epitaxial layer is facet-free and has a substantially uniform thickness on the amorphous layer and the fin top portion. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the fin bottom portion is in contact with the fin top portion and the epitaxial layer. 
     
     
         15 . The semiconductor device of  claim 12 , further comprising an isolation structure on the substrate and adjacent to the fin structure, wherein a top surface of the isolation structure is coplanar with the top surface of the fin bottom portion. 
     
     
         16 . A method, comprising:
 forming a dielectric layer on a substrate;   forming an amorphous layer on the dielectric layer;   forming a fin structure on the substrate; and   removing a sidewall portion of the fin structure to expose top surfaces of a bottom portion of the fin structure.   
     
     
         17 . The method of  claim 17 , further comprising conformally forming an epitaxial layer on the amorphous layer, sidewall surfaces of the fin structure, and the top surfaces of the bottom portion. 
     
     
         18 . The method of  claim 17 , wherein forming the fin structure comprises anisotropically etching the amorphous layer, the dielectric layer, and the substrate. 
     
     
         19 . The method of  claim 17 , wherein removing the sidewall portion of the fin structure comprises anisotropically etching the amorphous layer, the dielectric layer, and the fin structure. 
     
     
         20 . The method of  claim 17 , further comprising forming an isolation structure on the substrate and adjacent to the fin structure, wherein a top surface of the isolation structure is coplanar with the top surface of the bottom portion.