Semiconductor transistor with precise geometries and related manufacture method thereof

Abstract

A semiconductor transistor includes a semiconductor substrate with an original surface, an active region, a shallow trench isolation region, a shallow trench isolation region, a first conductive region and a second conductive region located within the active region, and a spacer. The active region is formed based on the semiconductor substrate and the active region has a fin structure. The shallow trench isolation region surrounds the active region and a gate structure of the semiconductor transistor crosses over the fin structure. The spacer contacts to a sidewall of the gate structure and on the fin structure. A width of the fin structure under the spacer is wider than that of the fin structure under the gate structure, the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure includes a rounded corner under the spacer.

What is claimed is: 
     
         1 . A semiconductor transistor comprising:
 a semiconductor substrate with an original surface;   an active region formed based on the semiconductor substrate, the active region having a fin structure;   a shallow trench isolation region surrounding the active region, and a gate structure of the semiconductor transistor crossing over the fin structure;   a first conductive region and a second conductive region of the semiconductor transistor located within the active region; and   a spacer contacted to a sidewall of the gate structure and on the fin structure;   wherein a width of the fin structure under the spacer is wider than that of the fin structure under the gate structure, the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure comprises a rounded corner under the spacer.   
     
     
         2 . The semiconductor transistor of  claim 1 , wherein the first conductive region is limited by the shallow trench isolation region, and a width of the first conductive region is wider than that of the fin structure under the gate structure. 
     
     
         3 . The semiconductor transistor of  claim 1 , wherein the fin structure comprises a fin body and a fin base, the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, and the perpendicular profile comprises a step-like transition or non-gradual transition between the fin body and the fin base. 
     
     
         4 . The semiconductor transistor of  claim 3 , wherein the lateral profile of the fin structure further provides another step-like transition or a non-gradual transition between the fin structure under the gate structure and the rounded corner. 
     
     
         5 . The semiconductor transistor of  claim 1 , wherein the first conductive region is contacted to a first end of the fin structure, the second conductive region is contacted to a second end of the fin structure, and the first conductive region and the second conductive region are independent from the fin structure. 
     
     
         6 . The semiconductor transistor of  claim 1 , wherein a bottom of the gate structure over the shallow trench isolation region is lower than a bottom of the first conductive region and/or the second conductive region. 
     
     
         7 . The semiconductor transistor of  claim 1 , wherein at least two sides of the first conductive region or the second conductive region are contacted to a metal-containing region. 
     
     
         8 . A semiconductor transistor comprising:
 a semiconductor substrate with an original surface;   an active region formed based on the semiconductor substrate, the active region having a fin structure;   a shallow trench isolation region surrounding the active region;   a gate structure of the semiconductor transistor crossing over the fin structure and covering a first portion of the shallow trench isolation region;   a first conductive region and a second conductive region of the semiconductor transistor located within the active region;   a canal along a longitudinal direction of the gate structure; and   an inner spacer filled in the contacted to a sidewall of the gate structure, wherein a width of the inner spacer limited by the canal;   wherein the fin structure comprises a fin body and a fin base, the fin body is covered by the gate structure, and the inner spacer at least covers sidewalls of the fin body.   
     
     
         9 . The semiconductor transistor of  claim 8 , wherein the inner spacer further covers portion sidewalls of the fin base. 
     
     
         10 . The semiconductor transistor of  claim 8 , wherein the inner spacer is a composite spacer comprises an oxide sub-spacer and a SiCOH sub-spacer surrounding sidewalls and a top surface of the oxide sub-spacer. 
     
     
         11 . The semiconductor transistor of  claim 8 , wherein at least two sides of the first conductive region or the second conductive region are contacted to a metal-containing region. 
     
     
         12 . The semiconductor transistor of  claim 8 , wherein a top surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than that of other portion of the shallow trench isolation region not covered by the gate structure. 
     
     
         13 . The semiconductor transistor of  claim 8 , wherein the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, the perpendicular profile of the fin structure provides a first step-like transition or non-gradual transition. 
     
     
         14 . The semiconductor transistor of  claim 13 , wherein the first step-like transition or non-gradual transition is between the fin body and the fin base. 
     
     
         15 . The semiconductor transistor of  claim 13 , wherein the fin structure has a lateral profile along a direction substantially parallel to the original surface, wherein the lateral profile of the fin structure provides a second step-like transition or non-gradual transition. 
     
     
         16 . The semiconductor transistor of  claim 15 , wherein the second step-like transition or non-gradual transition is between the gate structure and the first conductive region. 
     
     
         17 . The semiconductor transistor of  claim 16 , wherein the lateral profile of the fin structure further provides a third step-like transition or non-gradual transition which is between the gate structure and the second conductive region. 
     
     
         18 . The semiconductor transistor of  claim 8 , wherein the first conductive region and/or the second conductive region is limited by the shallow trench isolation region. 
     
     
         19 . The semiconductor transistor of  claim 8 , wherein a bottom of the gate structure over the first portion of the shallow trench isolation region is lower than that of the first conductive region and/or the second conductive region. 
     
     
         20 . The semiconductor transistor of  claim 8 , wherein the first conductive region and the second conductive region are independent from the fin structure and not over the shallow trench isolation region. 
     
     
         21 . A semiconductor transistor comprising:
 a semiconductor substrate with an original surface;   an active region formed based on the semiconductor substrate, the active region having a fin structure;   a shallow trench isolation region surrounding the active region;   a gate structure of the semiconductor transistor crossing over the fin structure and covering a first portion of the shallow trench isolation region;   a first conductive region and a second conductive region of the semiconductor transistor located within the active region; and   an inner spacer contacted to a sidewall of the gate structure;   wherein the fin structure comprises a fin body and a fin base, the fin body is covered by the gate structure; and the inner spacer at least covers sidewalls of the fin body;   wherein the fin structure has a perpendicular profile along a direction substantially perpendicular to the original surface, and the perpendicular profile of the fin structure provides a first step-like transition or non-gradual transition.   
     
     
         22 . The semiconductor transistor of  claim 21 , wherein the inner spacer further covers portion sidewalls of the fin base. 
     
     
         23 . The semiconductor transistor of  claim 21 , wherein the inner spacer is a composite spacer comprises an oxide sub-spacer and a SiCOH sub-spacer surrounding sidewalls and a top surface of the oxide sub-spacer. 
     
     
         24 . The semiconductor transistor of  claim 21 , wherein at least two sides of the first conductive region or the second conductive region are contacted to a metal-containing region. 
     
     
         25 . The semiconductor transistor of  claim 21 , wherein a top surface of the first portion of the shallow trench isolation region covered by the gate structure is lower than that of other portion of the shallow trench isolation region not covered by the gate structure. 
     
     
         26 . The semiconductor transistor of  claim 21 , wherein the first step-like transition or non-gradual transition is between the fin body and the fin base. 
     
     
         27 . The semiconductor transistor of  claim 21 , wherein the fin structure has a lateral profile along a direction substantially along to the original surface, wherein the lateral profile of the fin structure provides a second step-like transition or non-gradual transition. 
     
     
         28 . The semiconductor transistor of  claim 21 , wherein the first conductive region and/or the second conductive region is limited by the shallow trench isolation region. 
     
     
         29 . The semiconductor transistor of  claim 21 , wherein a bottom of the gate structure over the first portion of the shallow trench isolation region is lower than that of the first conductive region and/or the second conductive region. 
     
     
         30 . The semiconductor transistor of  claim 21 , wherein the first conductive region and the second conductive region are independent from the fin structure and not over the shallow trench isolation region. 
     
     
         31 . A manufacture method for a semiconductor transistor, comprising:
 based on a semiconductor substrate, forming a fin structure which comprises a fin body and a fin base;   forming a gate structure over the fin structure; forming a gate spacer over the fin structure; and   controlling a width of the fin body in the gate structure, such that the width of the fin body in the gate structure and outside the gate spacer is narrower than that of the fin body under the gate spacer, wherein the fin structure has a lateral profile along a direction substantially parallel to the original surface, and the lateral profile of the fin structure comprises a rounded corner under the gate spacer.   
     
     
         32 . The manufacture method of  claim 31 , wherein the Step of forming the fin structure comprises:
 defining the fin structure by a pad cover layer;   based on the pad cover layer, using a first etching process to etch the semiconductor substrate to form the fin body; and   forming a side spacer layer to cover sidewalls of the fin body; and based on the pad cover layer and the side spacer layer, using a second etching process to further etch the semiconductor substrate to form the fin base.   
     
     
         33 . The manufacture method of  claim 32 , wherein the Step of forming the gate structure comprises:
 forming a STI region to surround the fin structure, wherein a top surface of the STI region is higher than an original surface of the semiconductor substrate;   defining the gate structure by a patterned photo-resistance; and   etching down portion of the STI region and portion of the pad cover layer in the gate structure.   
     
     
         34 . The manufacture method of  claim 33 , wherein the Step of forming the gate spacer over the fin structure comprises:
 forming a polysilicon spacer covering sidewalls of the gate structure;   forming a TiN layer and a Tungsten material to fill in rest portion of the gate structure;   removing the polysilicon spacer to form canals in the gate structure; etching down the STI region within the canals; and   forming the gate spacer to fill in the canals; and removing the TiN layer and the Tungsten material.   
     
     
         35 . The manufacture method of  claim 34 , wherein the Step of controlling the width of the fin body in the gate structure comprises:
 etching down the STI region in the gate structure;   removing the side spacer layer within the gate structure to reveal sidewalls of the fin body; and   laterally etching the fin body, such that the width of the fin body in the gate structure and outside the gate spacer is narrower than that of the fin body under the gate spacer.   
     
     
         36 . The manufacture method of  claim 35 , further comprising:
 removing the pad cover layer within the gate structure to reveal a top surface of the fin body;   forming an EOT (Equivalent oxide Thickness) spacer on both the top surface and the sidewalls of the fin body; and   forming a gate structure to cover the top surface and the sidewalls of the fin body and the sidewall of the fin base in the gate structure; wherein the gate structure comprises a gate dielectric layer and a gate conductive layer covering the fin body, the fin base, and the STI region within the defined gate structure.   
     
     
         37 . The manufacture method of  claim 36 , further comprising:
 removing the pad cover layer outside the defined gate structure to reveal a first portion of the original surface of the semiconductor substrate; based on the first portion of the original surface, etching the semiconductor substrate to form a first trench; and   based on the first trench, forming a first conductive structure of the semiconductor transistor.   
     
     
         38 . The manufacture method of  claim 37 , wherein the Step of forming the first conductive structure comprises:
 forming a covering oxide layer based on the surface of the first trench; etching portion of the covering oxide layer to form a revealed sidewall of the semiconductor substrate;   forming a doped semiconductor structure based on the revealed sidewall of the semiconductor substrate, wherein the doped semiconductor structure is confined by the STI region; and   forming a metal structure to fill in the first trench and contact the doped semiconductor structure.   
     
     
         39 . The manufacture method of  claim 38 , wherein the doped semiconductor structure comprises a lightly doped semiconductor region and a highly doped semiconductor region.